Texas Instruments TMS320C6670 Data Manual page 164

TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689D—March 2012
Table 7-39 CIC0 Event Inputs — C66x CorePac Secondary Interrupts (Part 5 of 6)
Input Event# on CIC System Interrupt
167 Tracer_RAC_INTD
168 Tracer_RAC_FE_INTD
169 Tracer_TAC_INTD
170 MSMC_mpf_error4
171 MSMC_mpf_error5
172 MSMC_mpf_error6
173 MSMC_mpf_error7
174 MPU4_INTD
(MPU4_ADDR_ERR_INT and
MPU4_PROT_ERR_INT combined)
175 QM_INT_PASS_TXQ_PEND_31
176 QM_INT_CDMA_0
177 QM_INT_CDMA_1
178 RapidIO_INT_CDMA_0
179 PASS_INT_CDMA_0
180 TCP3D_C_ERROR
MPU5_INTD
(MPU5_ADDR_ERR_INT and
MPU5_PROT_ERR_INT combined)
181 SmartReflex_intrreq0
182 SmartReflex_intrreq1
183 SmartReflex_intrreq2
184 SmartReflex_intrreq3
185 VPNoSMPSAck
186 VPEqValue
187 VPMaxVdd
188 VPMinVdd
189 VPINIDLE
190 VPOPPChangeDone
191 Reserved
192 FFTC_A_INTD0
193 FFTC_A_INTD1
194 FFTC_A_INTD2
195 FFTC_A_INTD3
196 FFTC_B_INTD0
197 FFTC_B_INTD1
198 FFTC_B_INTD2
199 FFTC_B_INTD3
200 RACBDEVENT0
201 RACBDEVENT1
202 TCP3D_C_REVT0
203 TCP3D_C_REVT1
204 FFTC_C_ERROR0
205 FFTC_C_ERROR1
164 TMS320C6670 Peripheral Information and Electrical Specifications
Description
Tracer sliding time window interrupt for RAC
Tracer sliding time window interrupt for RAC_FE
Tracer sliding time window interrupt for TAC
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
MPU4 addressing violation interrupt and protection violation interrupt.
Queue Manager (Packet Accelerator) pend event
QM interrupt for CDMA starvation
QM interrupt for CDMA starvation
RapidIO interrupt for CDMA starvation
PASS interrupt for CDMA starvation
TCP3D_C_Error event
MPU5 Addressing violation interrupt and Protection violation interrupt.
SmartReflex sensor interrupt
SmartReflex sensor interrupt
SmartReflex sensor interrupt
SmartReflex sensor interrupt
VPVOLTUPDATE has been asserted but SMPS has not been responded to in a defined
time interval
SRSINTERUPT is asserted, but the new voltage is not different from the current SMPS
voltage
The new voltage required is equal to or greater than MaxVdd.
The new voltage required is equal to or less than MinVdd.
Indicating that the FSM of voltage processor is in idle.
Indicating that the average frequency error is within the desired limit.
FFTC_A error event and FFTC_A debug event
FFTC_A error event and FFTC_A debug event
FFTC_A error event and FFTC_A debug event
FFTC_A error event and FFTC_A debug event
FFTC_B error event and FFTC_B debug event
FFTC_B error event and FFTC_B debug event
FFTC_B error event and FFTC_B debug event
FFTC_B error event and FFTC_B debug event
RAC_B_debug Event
RAC_B_debug Event
TCP3d_C receive event0
TCP3d_C receive event1
FFTC_C Error event and FFTC_C debug event
FFTC_C Error event and FFTC_C debug event
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