Texas Instruments TMS320C6670 Data Manual page 218

TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689D—March 2012
7.34.3.1 IEEE 1149.1 JTAG Compatibility Statement
For maximum reliability, the C6670 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST
will always be asserted upon power up and the DSP's internal emulation logic will always be properly initialized
when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some
third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive TRST
high before attempting any emulation or boundary scan operations.
7.34.3.2 JTAG Electrical Data/Timing
Table 7-86 JTAG Test Port Timing Requirements
(see Figure 7-60)
No.
1 t Cycle time, TCK
c(TCK)
1a tw(TCKH) Pulse duration, TCK high (40% of tc)
1b tw(TCKL) Pulse duration, TCK low (40% of tc)
3 tsu(TDI-TCK) Input setup time, TDI valid to TCK high
3 tsu(TMS-TCK) Input setup time, TMS valid to TCK high
4 th(TCK-TDI) Input hold time, TDI valid from TCK high
4 th(TCK-TMS) Input hold time, TMS valid from TCK high
End of Table 7-86
Table 7-87 JTAG Test Port Switching Characteristics
(see Figure 7-60)
No.
2 t Delay time, TCK low to TDO valid
d(TCKL-TDOV)
End of Table 7-87
Figure 7-60 JTAG Test-Port Timing
TCK
TDO
3
TDI / TMS
218 TMS320C6670 Peripheral Information and Electrical Specifications
Parameter
1
1a 1b
2
4
Min
34
13.6
13.6
3.4
3.4
17
17
Min
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Max Unit
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Max Unit
13.6 ns