Texas Instruments TMS320C6670 Data Manual page 70

Multicore fixed and floating-point system-on-chip
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TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689D—March 2012
Table 3-2
Device State Control Registers (Part 3 of 4)
Address Start
Address End
0x0262025C
0x0262025F
0x02620260
0x0262027B
0x0262027C
0x0262027F
0x02620280
0x02620283
0x02620284
0x02620287
0x02620288
0x0262028B
0x0262028C
0x0262028F
0x02620290
0x02620293
0x02620294
0x02620297
0x02620298
0x0262029B
0x0262029C
0x0262029F
0x026202A0
0x026202BB
0x026202BC
0x026202BF
0x026202C0
0x026202FF
0x02620300
0x02620303
0x02620304
0x02620307
0x02620308
0x0262030B
0x0262030C
0x0262030F
0x02620310
0x02620313
0x02620314
0x02620317
0x02620318
0x0262031B
0x0262031C
0x0262031F
0x02620320
0x02620323
0x02620324
0x02620327
0x02620328
0x0262032B
0x0262032C
0x0262032F
0x02620330
0x02620333
0x02620334
0x02620337
0x02620338
0x0262033B
0x0262033C
0x0262033F
0x02620340
0x02620343
0x02620344
0x02620347
0x02620348
0x0262034B
0x0262034C
0x0262034F
0x02620350
0x02620353
0x02620354
0x02620357
0x02620358
0x0262035B
0x0262035C
0x0262035F
0x02620360
0x02620363
0x02620364
0x02620367
0x02620368
0x0262036B
0x0262036C
0x0262036F
0x02620370
0x02620373
70
Device Configuration
Size
Acronym
4B
Reserved
28B
Reserved
4B
IPCGRH
4B
IPCAR0
4B
IPCAR1
4B
IPCAR2
4B
IPCAR3
4B
Reserved
4B
Reserved
4B
Reserved
4B
Reserved
28B
Reserved
4B
IPCARH
64B
Reserved
4B
TINPSEL
4B
TOUTPSEL
4B
RSTMUX0
4B
RSTMUX1
4B
RSTMUX2
4B
RSTMUX3
4B
Reserved
4B
Reserved
4B
Reserved
4B
Reserved
4B
MAINPLLCTL0
4B
MAINPLLCTL1
4B
DDR3PLLCTL0
4B
DDR3PLLCTL1
4B
PASSPLLCTL0
4B
PASSPLLCTL1
4B
SGMII_SERDES_CFGPLL
4B
SGMII_SERDES_CFGRX0
4B
SGMII_SERDES_CFGTX0
4B
SGMII_SERDES_CFGRX1
4B
SGMII_SERDES_CFGTX1
4B
Reserved
4B
PCIE_SERDES_CFGPLL
4B
Reserved
4B
SRIO_SERDES_CFGPLL
4B
SRIO_SERDES_CFGRX0
4B
SRIO_SERDES_CFGTX0
4B
SRIO_SERDES_CFGRX1
4B
SRIO_SERDES_CFGTX1
Description
See section
3.3.14
See section
3.3.13
See section
3.3.15
See section
3.3.16
See section
3.3.17
See section
3.3.18
See section 7.5
''Main PLL and the PLL Controller''
See section 7.6
''DDR3 PLL''
on page 142
See section 7.7
''PASS PLL''
on page 144
See
''Related Documentation from Texas Instruments''
Copyright 2012 Texas Instruments Incorporated
Submit Documentation Feedback
www.ti.com
on page 128
on page 66

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