Texas Instruments TMS320C6670 Data Manual page 166

TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689D—March 2012
Table 7-40 CIC1 Event Inputs (Secondary Events for EDMA3CC1 and EDMA3CC2) (Part 2 of 4)
Input Event # on CIC System Interrupt
37 QM_INT_HIGH_29
38 QM_INT_HIGH_30
39 QM_INT_HIGH_31
40 MDIO_LINK_INTR0
41 MDIO_LINK_INTR1
42 MDIO_USER_INTR0
43 MDIO_USER_INTR1
44 MISC_INTR
45 TRACER_CORE_0_INTD
46 TRACER_CORE_1_INTD
47 TRACER_CORE_2_INTD
48 TRACER_CORE_3_INTD
49 TRACER_DDR_INTD
50 TRACER_MSMC_0_INTD
51 TRACER_MSMC_1_INTD
52 TRACER_MSMC_2_INTD
53 TRACER_MSMC_3_INTD
54 TRACER_CFG_INTD
55 TRACER_QM_SS_CFG_INTD
56 TRACER_QM_SS_DMA_INTD
57 TRACER_SEM_INTD
58 SEMERR0
59 SEMERR1
60 SEMERR2
61 SEMERR3
62 BOOTCFG_INTD
63 PASS_INT_CDMA_0
64 MPU0_INTD
(MPU0_ADDR_ERR_INT and
MPU0_PROT_ERR_INT combined)
65 MSMC_SCRUB_CERROR
66 MPU1_INTD
(MPU1_ADDR_ERR_INT and
MPU1_PROT_ERR_INT combined)
67 RapidIO_INT_CDMA_0
68 MPU2_INTD
(MPU2_ADDR_ERR_INT and
MPU2_PROT_ERR_INT combined)
69 QM_INT_CDMA_0
70 MPU3_INTD
(MPU3_ADDR_ERR_INT and
MPU3_PROT_ERR_INT combined)
71 QM_INT_CDMA_1
72 MSMC_DEDC_CERROR
73 MSMC_DEDC_NC_ERROR
74 MSMC_SCRUB_NC_ERROR
75 Reserved
166 TMS320C6670 Peripheral Information and Electrical Specifications
Description
QM interrupt
QM interrupt
QM interrupt
PASS_MDIO interrupt
PASS_MDIO interrupt
PASS_MDIO interrupt
PASS_MDIO interrupt
PASS_MISC interrupt
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for DDR3 EMIF1
Tracer sliding time window interrupt for MSMC SRAM bank0
Tracer sliding time window interrupt for MSMC SRAM bank1
Tracer sliding time window interrupt for MSMC SRAM bank2
Tracer sliding time window interrupt for MSMC SRAM bank3
Tracer sliding time window interrupt for CFG0 SCR
Tracer sliding time window interrupt for QM_SS CFG
Tracer sliding time window interrupt for QM_SS slave port
Tracer sliding time window interrupt for Semaphore
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Chip-level MMR interrupt
PASS Interrupt for CDMA starvation
MPU0 addressing violation interrupt and protection violation interrupt.
Correctable (1-bit) soft error detected during scrub cycle
MPU1 addressing violation interrupt and protection violation interrupt.
RapidIO interrupt for CDMA starvation
MPU2 addressing violation interrupt and protection violation interrupt.
QM Interrupt for CDMA starvation
MPU3 addressing violation interrupt and protection violation interrupt.
QM interrupt for CDMA starvation
Correctable (1-bit) soft error detected on SRAM read
Non-correctable (2-bit) soft error detected on SRAM read
Non-correctable (2-bit) soft error detected during scrub cycle
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