Figure 2-5 Ethernet (Sgmii) Device Configuration Fields - Texas Instruments TMS320C6670 Data Manual

TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689D—March 2012
2.4.2.3 Ethernet (SGMII) Boot Device Configuration
Figure 2-5 Ethernet (SGMII) Device Configuration Fields
9
SerDes Clock Mult
Table 2-6 Ethernet (SGMII) Configuration Field Descriptions
Bit Field
9-8 SerDes clock mult
7-6 Ext connection
5-3 Device ID
End of Table 2-6
2.4.2.4 PCI Boot Device Configuration
Additional device configuration is provided in the PCI bits in the DEVSTAT register.
Figure 2-6 PCI Device Configuration Fields
9
Reserved
Table 2-7 PCI Device Configuration Field Descriptions
Bit Field
9 Reserved
8-5 Bar Config
4-3 Reserved
End of Table 2-7
32 Device Overview
8 7
Ext connection
Description
SGMII SerDes input clock. The output frequency of the PLL must be 1.25 GBs.
0 = ×8 for input clock of 156.25 MHz
1 = ×5 for input clock of 250 MHz
2 = ×4 for input clock of 312.5 MHz
3 = Reserved
External connection mode
0 = MAC to MAC connection, master with auto negotiation
1 = MAC to MAC connection, slave, and MAC to PHY
2 = MAC to MAC, forced link
3 = MAC to fiber connection
This value can range from 0 to 7 and is used in the device ID field of the Ethernet-ready frame.
8 7
BAR Config
Description
Reserved
PCIe BAR registers configuration
This value can range from 0 to 0xf. See
Reserved
6 5
6 5
Table 2-8.
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4 3
Dev ID
4 3
Reserved
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