Texas Instruments TMS320C6670 Data Manual page 121

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Table 7-8 PSC Register Memory Map (Part 3 of 3)
Offset Register
0xA14 MDCTL5
0xA18 MDCTL6
0xA1C MDCTL7
0xA20 MDCTL8
0xA24 MDCTL9
0xA28 MDCTL10
0xA2C MDCTL11
0xA30 MDCTL12
0xA34 MDCTL13
0xA38 MDCTL14
0xA3C MDCTL15
0xA40 MDCTL16
0xA44 MDCTL17
0xA48 MDCTL18
0xA4C MDCTL19
0xA50 MDCTL20
0xA54 MDCTL21
0xA58 MDCTL22
0xA5C MDCTL23
0xA60 MDCTL24
0xA64 MDCTL25
0xA68 MDCTL26
0xA6C MDCTL27
0xA70 MDCTL28
0xA74 MDCTL29
0xA78 MDCTL30
0xA7C - 0xFFC Reserved
End of Table 7-8
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Multicore Fixed and Floating-Point System-on-Chip
Description
Module Control Register 5 (debug subsystem and tracers)
Module Control Register 6 (per-CorePac TETB and system TETB)
Module Control Register 7 (Packet Accelerator)
Module Control Register 8 (Ethernet SGMIIs)
Module Control Register 9 (Security Accelerator)
Module Control Register 10 (PCIe)
Module Control Register 11 (SRIO)
Module Control Register 12 (HyperLink)
Module Control Register 13 (Reserved)
Module Control Register 14 (MSMC RAM)
Module Control Register 15 (RAC_A and RAC_B)
Module Control Register 16 (TAC)
Module Control Register 17 (FFTC_A and FFTC_B)
Module Control Register 18 (AIF2)
Module Control Register 19 (TCP3d_A)
Module Control Register 20 (VCP2_B)
Module Control Register 21 (VCP2_C)
Module Control Register 22 (VCP2_D)
Module Control Register 23 (C66x CorePac0 and Timer 0)
Module Control Register 24 (C66x CorePac1and Timer 1)
Module Control Register 25 (C66x CorePac1 RSAs)
Module Control Register 26 (C66x Corepac2 and Timer 2)
Module Control Register 27 (C66x CorePac2 RSAs)
Module Control Register 28 (C66x CorePac3 and Timer 3)
Module Control Register 29 (TCP3d_B)
Module Control Register 30(BCP, FFTC_C and TCP3d_C)
Reserved
TMS320C6670 Peripheral Information and Electrical Specifications
TMS320C6670
SPRS689D—March 2012
121