Texas Instruments TMS320C6670 Data Manual page 42

TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689D—March 2012
Table 2-15 Terminal Functions — Signals and Control by Function (Part 2 of 12)
Signal Name Ball No. Type IPD/IPU Description
AIFTXN0 L26
AIFTXP0 M26
AIFTXN1 L27
AIFTXP1 K27
AIFTXN2 R26
AIFTXP2 P26
AIFTXN3 P27
AIFTXP3 N27
AIFTXN4 U27
AIFTXP4 T27
AIFTXN5 U26
AIFTXP5 V26
RP1CLKP Y28
RP1CLKN AA28
EXTFRAMEEVENT AE17
RP1FBP Y29
RP1FBN AA29
PHYSYNC AB27
RADSYNC AA27
LENDIAN † AJ20
BOOTMODE00 † AG18
BOOTMODE01† AD19
BOOTMODE02 † AE19
BOOTMODE03 † AF18
BOOTMODE04 † AE18
BOOTMODE05 † AG20
BOOTMODE06 † AH19
BOOTMODE07 † AJ19
BOOTMODE08 † AE21
BOOTMODE09 † AG19
BOOTMODE10 † AD20
BOOTMODE11 † AE20
BOOTMODE12 † AF21
PCIESSMODE0 † AH20
PCIESSMODE1 † AD21
PCIESSEN † AJ23
SYSCLKP AC29
SYSCLKN AC28
PASSCLKP AJ18
PASSCLKN AH18
42 Device Overview
O
O
O
O
O
O
Antenna interface transmit data (6 links)
O
O
O
O
O
O
AIF2 Timer (AT) Module
I
Frame sync interface clock used to drive the frame synchronization interface (OBSAI RP1 clock)
I
Frame sync clock output
OZ Down
I
Frame burst to drive frame indicators to the frame synchronization module (OBSAI RP1)
I
Frame sync input for PHY timer
I Down
Frame sync input for radio timer
I Down
Boot Configuration Pins
IOZ Up Endian configuration pin (pin shared with GPIO[0])
IOZ Down
IOZ Down
IOZ Down
IOZ Down
IOZ Down
IOZ Down
See Section 2.4
IOZ Down
(Pins shared with GPIO[1:13])
IOZ Down
IOZ Down
IOZ Down
IOZ Down
IOZ Down
IOZ Down
IOZ Down
PCIe mode selection pins (pins shared with GPIO[14:15])
IOZ Down
I PCIe module enable (pin shared with TIMI0)
I
System clock input to antenna interface and/or main PLL
I
I
Network coprocessor reference clock to PASS PLL
I
''Boot Modes Supported and PLL Settings''
Clock / Reset
on page 30 for more details
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