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Each time data is written to or read from ISA I/O offset 00Fh, this must be
preceded by a write of 03h to ISA I/O offset 0Dh. This is to prevent accidental
use of the watchdog timer. The index register is always reset to 00h after a read
or write to I/O offset 00Fh.
The strobe register is at I/O offset 00Bh. A write to ISA I/O offset 00Bh will
reset the watchdog timer to the delay value in the watchdog register. The status
of the WD (watchdog) bit is read at ISA I/O offset 00Bh.
Bit
7
Function
Clear watchdog
Bit 7 - clear watchdog bit
This bit at logic 1 will clear the watchdog timer function. This bit has to be
written with a 0 to start the watchdog timer. When the watchdog flag in the I/O
Port offset 0Bh (Read) is set, the flag can only be reset by a write of a 1 to this
register.
Bits 4-3 watchdog mode
These two bits control the mode of the watchdog timer.
Data
00
Disable the watchdog timer
01
Set the watchdog flag when timer counts to zeroes
10
Set the watchdog flag and assert IOCHRDY when the timer counts to zeroes
11
Set the watchdog flag and assert IOCHRDY and RESET the CPV5000 when
the timer counts to zeroes
FPGA Access, Watchdog and ENUM registers
Table 4-15. Watchdog register
6
5
4
Reserved
Watchdog mode
Table 4-16.
Watchdog mode
Mode
3
2
1
Watchdog delay mode
4
0
4-21
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