Chipset Setup; Memory Hole; Irq12/M Mouse Function; Dram Speed - Motorola CPV5000 Installation And Reference Manual

Compactpci single board computer
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WinBIOS Setup

Chipset setup

This section describes the setup of the memory timings for the CPV5000.
These setting can significantly affect the performance and reliability of the
CPV5000. Motorola recommends that you use the default optimal settings.

Memory hole

Use this option to specify an area in memory that cannot be addressed on the
ISA bus. The settings are Disabled, 512 to 640 KB, or 15 to 16 MB. Accesses
to memory holes are automatically forwarded to PCI.

IRQ12/M mouse function

Set this option to Enabled to specify that IRQ12 will be used for the mouse.
The settings are Disabled or Enabled.
7

DRAM speed

Specify the RAS access speed of the SIMMs installed in the CPV5000 as
system memory. The settings are 60 ns or 70 ns. The default is 70 ns. Manual
setting is not supported.

Refresh rate

This option is only available in manual DRAM setup. The DRAM refresh rate
is adjusted to the frequency selected by this field. The options are for 50 MHz,
60 MHz, or 66 MHz.

Turbo lead readoff

This option is only available in manual DRAM setup. This option can be
enabled to bypass the first input register in the DRAM data pipeline. This
results is a reduction of one clock cycle from the read leadoff timing.
7-16
Note
If you have installed SIMMS with different speeds in the
CPV5000, select the speed of the slowest SIMM. You must
always use SIMMS that have the same speed within a
memory bank.

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