Motorola CPCI-6115 Installation And Use Manual

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CPCI-6115 CompactPCI
Single Board Computer
Installation and Use
6806800A68D
March 2008

   Summary of Contents for Motorola CPCI-6115

  • Page 1

    CPCI-6115 CompactPCI Single Board Computer Installation and Use 6806800A68D March 2008...

  • Page 2

    Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.

  • Page 3: Table Of Contents

    2.7.1 Installing PMC Modules on the CPCI-6115 ........

  • Page 4: Table Of Contents

    ABORT/Reset Switch ........

  • Page 5: Table Of Contents

    5.5.7 RJ-45 to DB-9 Adapter for COM1 to PC COM1 ......101 CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)

  • Page 6: Table Of Contents

    Memory Maps ............. 125 CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)

  • Page 7: Table Of Contents

    A.3 Related Specifications ............132 CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)

  • Page 8

    Contents CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)

  • Page 9: List Of Tables

    Table 5-1 CPCI-6115-MCPTM Rear Panel Connectors ....... . 92 Table 5-2 On-Board Connectors and Headers .

  • Page 10

    Motorola ECC Documents ........

  • Page 11: List Of Figures

    CPCI-6115-MCPTM Serial Ports 1 and 2 ....... . . 108...

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    List of Figures CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)

  • Page 13: About This Manual

    MCPN905. Chapter 5, Transition Module Preparation and module that is compatible with the CPCI-6115. Information includes a brief overview, unpacking instructions, board preparation and installation instructions, face plate and on-board connector descriptions and pin assignments. Other sections describe the functionality, the PIMs that are installed on the transition module, along with installation and removal instructions.

  • Page 14

    About this Manual Appendix A, Related produced by Motorola, as well as third parties. It also provides a list of industry related specifications. Abbreviations This document uses the following abbreviations: Abbreviation ASIC CBGA CHRP CPCI DRAM EIDE ETSI IDMA CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)

  • Page 15

    NVRAM PCI-X PICMG PMCIO PrPMC RISC RTOS RoHS CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Description Institute of Electrical and Electronics Engineers, Inc. I/O Signal Multiplexing Internet Protocol Light Emitting Diode LED On/OFF Media Access Control Multipurpose Port...

  • Page 16

    Screen Courier + Bold Reference File > Exit <text> [text] CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Description Space-Division Multiple Access Synchronous Dynamic Random Access Memory Safety Extra Low Voltage Serial Presence Detect Static Random Access Memory...

  • Page 17

    Applied new documentation style standards throughout. March 2007 Corrected default setting for J99 CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) About this Manual Description Ranges, for example: 0..4 means one of the integers 0,1,2,3, and 4 (used in registers)

  • Page 18

    About this Manual Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation. We want to know what you think about our manuals and how we can make them better. Mail comments to: Embedded Communications Computing Reader Comments DW164 2900 S.

  • Page 19: Safety Notes

    Motorola intends to provide all necessary information to install and handle the product in this manual. Because of the complexity of this product and its various uses, we do not guarantee that the given information is complete.

  • Page 20

    Incorrect installation or removal of additional devices or modules may damage the product or the additional devices or modules. Before installing or removing additional devices or modules, read the respective documentation. CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)

  • Page 21

    Inserting or removing modules in a non-hot-swap chassis with power applied may result in damage to module components. The CPCI-6115 is a hot-swappable board and may be inserted in a hot-swap chassis, such as a CPX2000, CPX8000 or MXP3000 series chassis with power applied.

  • Page 22

    Il y a danger d’explosion s’il y a remplacement incorrect de la batterie. Remplacer uniquement avec une batterie du même type ou d’un type équivalent recommandé par le constructeur. Mettre au rebut les batteries usagées conformément aux instructions du fabricant. CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)

  • Page 23: Sicherheitshinweise

    Installieren Sie keine Ersatzteile oder führen Sie keine unerlaubten Veränderungen am Produkt durch, sonst verfällt die Garantie. Wenden Sie sich für Wartung oder Reparatur bitte an die für Sie zuständige Geschäftsstelle von Motorola. So stellen Sie sicher, dass alle sicherheitsrelevanten Aspekte beachtet werden.

  • Page 24

    Störungen auslösen. Verstellen Sie nur solche Schalter, die nicht mit 'Reserved' gekennzeichnet sind. Prüfen und ggf. ändern Sie die Einstellungen der nicht mit 'Reserved' gekennzeichneten Schalter, bevor Sie das Produkt installieren. CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)

  • Page 25

    Spannungsversorgung eingeschaltet ist und das nicht Hot-Swap-fähig ist, kann das Modul beschädigt werden. Das CPCI-6115 ist ein Hot-Swap-fähiges Board und kann in ein Hot-Swap-fähiges Chassis, dessen Spannungsversorgung eingeschaltet ist, installiert werden. Beispiele für derartige Chassis sind solche aus der Serie CPX2000, CPX8000 oder MXP3000.

  • Page 26

    Ihrem Land gültigen Gesetzgebung und den Empfehlungen des Herstellers. Batterie Beschädigung des Produktes Explosionsgefahr bei unsachgemäßem Austausch der Batterie. Ersatz nur durch denselben oder einen vom Hersteller empfohlenen Typ. Entsorgung gebrauchter Batterien nach Angaben des Herstellers. CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)

  • Page 27: Features, Introduction

    Introduction Features The following table summarizes the features of the CPCI-6115 Single Board Computer (SBC). The CPCI-6115 was formerly offered as the MCPN905 SBC. Table 1-1 CPCI-6115 Features Feature Processor L3 Cache Flash SDRAM Memory Controllers PCI Host Bridges Interrupt Controller...

  • Page 28: Standard Compliances

    Feature Watchdog Timers Peripheral Support PMC Slots Front Panel Debug Support Standard Compliances The CPCI-6115 is designed to be CE compliant and to meet the following standard requirements. Table 1-2 Board Standard Compliances Standard UL 60950-1 EN 60950-1 IEC 60950-1 CAN/CSA C22.2 No 60950-1...

  • Page 29: Ordering Information

    CPCI-6115-270 Table 1-4 Related Product Order Numbers Related Products CPCI-6115-MCPTM-02 CFLASH5E-xxx CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Description Environmental Requirements Directive on the restriction of the use of certain hazardous substances in electrical and electronic equipment (RoHS)

  • Page 30

    Introduction Ordering Information CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)

  • Page 31: Overview, Unpacking And Inspecting The Board, Hardware Preparation And Installation

    PMCs and transition module associated with this board. The CPCI-6115 can be used in both a CompactPCI or a PICMG 2.16 compatible chassis. It can be used only in a peripheral (nonsystem) slot. The board employs an Intel 21555 PCI-to-PCI bridge for accessing additional components on adjacent PCI buses.

  • Page 32: Environmental, Power, And Thermal Requirements, Environmental Requirements

    Environmental Requirements The following table lists the currently available specifications for the environmental and mechanical characteristics of the CPCI-6115. A complete functional description of the CPCI- 6115 baseboard appears in PCI mezzanines can be found in the documentation for those modules.

  • Page 33

    Do not operate the board outside the specified environmental limits. Make sure the board is completely dry and there is no moisture on any surface before applying power. CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Hardware Preparation and Installation Specifications –40°C to +70°...

  • Page 34: Power Requirements, Thermal Requirements

    These operating conditions vary depending on system design. While Motorola performs thermal analysis in a representative system to verify operation within specified ranges (see the board in your application.

  • Page 35

    U23, U89 U159, U160 U146 U13, U14 U2-U10, U74-U82 U101, U102, U96 CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) summarizes components that exhibit significant temperature rises. These General Description Ultra DMA PCI-IDE 21555BB PCI Bridge MPC7457 Processor DDR Clock Generator...

  • Page 36

    Hardware Preparation and Installation Figure 2-1 CPCI-6115 Thermally Significant Components (Primary Side) CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) U159 U160 U146 Thermal Requirements...

  • Page 37: Getting Started, Overview Of Start-up Procedure

    Task Unpack the hardware Configure the hardware by setting jumpers on the baseboard and transition module. CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Section or Manual Reference Unpacking and Inspecting the Board Setting Switches and Jumpers Jumper Settings...

  • Page 38: Equipment Required, Baseboard Preparation, Configuring The Hardware, Transition Module Preparation And Installation

    Disk drives (and/or other I/O) and controllers The CPCI-6115 baseboards are factory-configured for I/O handling via its front panel, installed PMCs or a rear transition module that is specifically designed for the CPCI-6115 product family. Baseboard Preparation This section discusses certain hardware and software tasks that may need to be performed prior to installing the board in a CompactPCI or PICMG 2.9 compliant chassis.

  • Page 39: Setting Switches And Jumpers

    Setting Switches and Jumpers Figure 2-2 on page 35 and LED indicators on the CPCI-6115. Use this figure to help identify the approximate location of the jumpers on the CPCI-6115. There are seven manually configured headers on the baseboard. They are described in the following table:...

  • Page 40: J6, Bus Mode Selection

    MPX). No jumper or a jumper between pins 2 and 3 allows the board to be in MPX mode. A jumper placed between pins 1 and 2 enables 60x mode. Figure 2-4 Jumper Setting for J6 CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) J6, Bus Mode Selection...

  • Page 41: J9, Standalone Operating Mode, J10, Flash Bank Selection

    The J9 jumper must be removed for normal operation. Figure 2-5 Jumper Settings for J9 An CPCI-6115 configured for standalone mode should not be installed in a chassis with a system slot controller board. This will result in unpredictable system operation. 2.5.5 J10, Flash Bank Selection The flash memory is organized in two banks (A and B).

  • Page 42: J15, +/-12 V Present Header, J20, Safe Start Header

    A jumper placed between pins 2 and 3 allows the safe start settings (Safe VPD, SPD parameters, GEVs ignored) to be used. Figure 2-8 Jumper Setting for J20 CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) J15, +/-12 V Present Header...

  • Page 43: J25, Srom Initialization Enable Header, J99, Flash Bank A Programming Enable Header

    No jumper installed disables all Flash Bank A programming. Figure 2-10 Jumper Setting for J99 CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Hardware Preparation and Installation C SROM. No jumper or a jumper placed...

  • Page 44: Sw2, Geographic Address, Operating Modes, Installing Hardware

    An CPCI-6115 configured for the standard operating mode must be used in a chassis with a system slot board which provides the clock and arbitration signals to the CPCI-6115. The chassis must provide +5 V, +3.3 V and VIO to the CPCI-6115, and the BD_SEL pin (P1- D15) in the chassis must be grounded.

  • Page 45: Installing Pmc Modules On The Cpci-6115

    In most cases, PMC modules ordered with the baseboard are installed on the CPCI-6115 at the factory and the order is shipped as a single unit. The user-configured jumpers on the PMCs are accessible with the modules installed.

  • Page 46

    Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing and adjusting. 3. Carefully remove the CPCI-6115 from the card slot and lay it flat, with connectors J1 through J5 facing you. 4. Remove the PMC filler plate from the front panel of the CPCI-6115.

  • Page 47

    CPCI-6115 into the PMC front bezel and rear standoffs. Tighten the screws. 8. Reinstall the CPCI-6115 assembly in its proper card slot. Be sure the module is well seated in the backplane connectors. Do not damage or bend connector pins.

  • Page 48: Installing The Cpci-6115 Baseboard

    Use extreme caution when handling, testing and adjusting. 3. Remove the filler panel from the appropriate card slot. 4. Set the VIO on the backplane to either +3.3 V or +5 V (the CPCI-6115 is a universal board), depending upon your CompactPCI system signaling requirements and ensure the backplane does not bus J3 or J5 signals.

  • Page 49: Connecting To A Console Port, Applying Power

    Parity disabled (no parity) Baud rate of 9600 9600 baud is the power-up default for serial ports on CPCI-6115 boards. After power-up you can reconfigure the baud rate if you wish, using the MOTLoad PF (Port Format) command via the command line interface. Whatever the baud rate, some type of hardware handshaking —...

  • Page 50

    (BFL, CPU, and HOT SWAP STATUS). For more information on front panel operation, refer to Chapter 4, Functional The CPCI-6115 also has status LEDs for SPEED/LINK and ACTIVITY for Ethernet 2 on the front panel. CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)

  • Page 51: Controls, Leds, And Connectors, Overview

    This chapter illustrates the placement of the on-board jumper headers and connectors as well as the front panel connectors and LED indicators on the CPCI-6115. Also included are the pin assignments for the connectors and headers on the CPCI-6115 CompactPCI Single Board Computer.

  • Page 52: Board Layout, Front Panel Connectors And Leds

    Figure 3-1 Component Layout Front Panel Connectors and LEDs The CPCI-6115 CPU board provides these status LEDs visible on the front panel of the CPCI- 6115. Table 3-1 Front Panel LEDs Indicator Color Green...

  • Page 53

    Blue SPD/LNK Green/Yellow Green The CPCI-6115 front panel provides also provides a recessed Abort/Reset push-button switch, an RJ-45 Ethernet connector with status LEDs, an RJ-45 asynchronous serial port connector and, two PMC cutouts. Figure 3-2 Front Panel Connector Cutouts, Connectors, and LED Indicators...

  • Page 54: Abort/reset Switch, On-board Connectors And Headers, J19, Front Panel Asynchronous Serial Port

    J19, Front Panel Asynchronous Serial Port An RJ-45 receptacle is located on the front panel of the CPCI-6115 CPU board to provide the interface to the COM1 serial port. This port is configured as DTE. The pin assignments for this...

  • Page 55: J95, Front Panel 10/100/1000 Megabits/s Ethernet Connector, Compactpci J1/j2 Connectors

    Pin # 3.5.2 J95, Front Panel 10/100/1000 Megabits/s Ethernet Connector The CPCI-6115 has one front panel 10/100/1000 megabit/s Gigabit Ethernet connector. It is an industry standard RJ-45 connector with the following pin assignments: Table 3-3 10/100/1000 Megabit/s Ethernet Connector, J95...

  • Page 56: Compactpci Bus Connector

    Controls, LEDs, and Connectors 3.5.4 CompactPCI Bus Connector Pinouts for the J1 CompactPCI Bus connector on the CPCI-6115 are as follows: Table 3-4 CompactPCI Connector, J1 Row A +5.0 V AD[1] +3.3 V AD[7] +3.3 V AD[12] +3.3 V SERR# +3.3 V...

  • Page 57: Compactpci User I/o Connector

    AD[63] C/BE[5]# V(IO) a. Defined as SYSEN#. This OV allows the CPCI-6115 to ensure that it is installed into a peripheral slot. 3.5.6 CompactPCI User I/O Connector Connector J3 is a 110 pin AMP Z-pack 2mm hard metric type B connector. This connector routes the I/O signals for one of the PMC slots and two 10/100/1000Base-T Ethernet channels compliant with the CompactPCI Packet Switching Backplane Specification.

  • Page 58: Compactpci Connector

    LPb_Dx PMC User I/O: PMCIO(64:1) 3.5.7 CompactPCI Connector There are no electrical connections from the CompactPCI J4 connector to the CPCI-6115. This connector is depopulated. CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Row B Row C +3.3 V +3.3 V...

  • Page 59

    PMCIO35 PMCIO40 PMCIO45 PMCIO50 PMCIO55 PMCIO60 TM_PRSNT# Signal Descriptions IDE Port, TTL Levels: DMARQ DMACK_L DIOR_L CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Row B Row C Row D COM2_TXD COM2_RXD CS3FX# (CS1) MXDI DIORDY MXCLK TMCOM1# I2C_CLK...

  • Page 60

    PMCIO(64:1) Miscellaneous TM_PRSNT# I2C_CLK I2C_DATA No Connect CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) I/O write indicates drive ready for I/O data lines reset signal to drive chip select drive 0 or command register block select chip select drive 1 or command register block select...

  • Page 61: Pci Mezzanine Card (pmc) Connectors

    3.5.9 PCI Mezzanine Card (PMC) Connectors There are four 64-pin EIA E700 AAAB SMT connectors for each PMC slot on the CPCI-6115 to provide the two 32/64-bit PCI interface and optional I/O interface to the PMC. When the front-panel Gigabit Ethernet is populated, PMC 1 has a 32-bit interface. In this case, these pins are not connected on J13.

  • Page 62

    AD16 TRDY# PERR# +3.3 V C/BE1# AD14 M66EN AD08 AD07 +3.3 V MOT_RSVD MOT_RSVD CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) PCI Mezzanine Card (PMC) Connectors J11/J21 +5 V REQ64# TRST# PCI_RSVD PCI_RSVD +3.3 V MOT_RSVD MOT_RSVD AD29 AD26 +3.3 V...

  • Page 63

    AD47 (Note 1) AD45 (Note 1) AD43 (Note 1) AD41 (Note 1) AD39 (Note 1) AD37 (Note 1) CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Controls, LEDs, and Connectors NC (RESETOUT_L) +3.3 V NC (MONARCH#) Motorola Reserved pin...

  • Page 64

    PMCIO29 PMCIO31 PMCIO33 PMCIO35 PMCIO37 PMCIO39 PMCIO41 PMCIO43 PMCIO45 PMCIO47 PMCIO49 CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) PCI Mezzanine Card (PMC) Connectors J13/J23 AD36 (Note 1) AD34 (Note 1) AD32 (Note 1) PCI_RSVD PCI_RSVD J14/J24 PMCIO2 PMCIO4...

  • Page 65: Boundary Scan Jtag Header, Processor Jtag/cop Header

    The pin assignments for this header are as follows: With no JTAG cable attached to J16, the CPU JTAG signals are routed to J17 as shown. Table 3-13 Processor JTAG/COP Header Pin Assignments, J17 CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) J14/J24 PMCIO52...

  • Page 66: Stand-alone Operation Select Header, Flash Boot Bank Select Header

    Flash Boot Bank Select Header There is a 0.1", 3-pin header on the CPCI-6115 to select the boot flash bank. No jumper or a jumper installed between pins 1 and 2 will route the BOOTCS* signal to Flash Bank A and device CS0* to Flash Bank B.

  • Page 67: Safe Start Header, Bus Mode Select Header, Srom Initialization Enable Header

    Table 3-18 SROM Initialization Enable Header Pin Assignments, J25 Signal +3.3 V SROM_INIT CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Controls, LEDs, and Connectors Function 1-2 for ENV parameters 2-3 for SAFE start...

  • Page 68: Flash Bank A Write Protect Header, V Present Header

    3.5.18 +/-12 V Present Header A 2-pin 0.1" header is located on the board to inform the CPCI-6115 whether the +/-12 V power supplies are present on the backplane. If so, then these power supplies are monitored for inclusion in the HLTY# status. If no jumper is installed, the CPCI-6115 will assume that the +/- 12 V supplies are present.

  • Page 69: Functional Description, Overview

    Functional Description Overview This chapter describes the CPCI-6115 single-board computer on a block diagram level. The General Description section provides an overview of the CPCI-6115, followed by a detailed description of several blocks of circuitry. architecture. Detailed descriptions of other CPCI-6115 blocks, including programmable registers in the ASICs and peripheral chips, can be found in the MCPN905 CompactPCI Single Board Computer Programmer’s Reference Guide and the Marvell MV64360 Reference Guide, both...

  • Page 70: Block Diagram

    Functional Description Block Diagram The block diagram below illustrates the architecture of the CPCI-6115 baseboard. Figure 4-1 CPCI-6115 Baseboard Block Diagram L2 Cache Private Memory 1MB/2MB 60x or MPX Bus 133 MHz Flash A 32MB Flash B NVRAM Device Bus...

  • Page 71: General Description, Processor Bus Resources

    MV64360 PCI-Host bridge/system memory controller and the Intel 21555 PCI-to- PCI bridge. The CPCI-6115 supports up to 1.5 GB of DDR SDRAM, two PMC sites, 8MB of boot flash, 32MB of soldered flash, three Gigabit Ethernet ports and one IDE port. The CPCI- 6115 also supports the CompactPCI Packet Switching Backplane (PICMG 2.16) specification.

  • Page 72: Processor, L3 Cache, Mv64360 System Controller

    The MPC7457 processors have integrated L1 and L2 caches and has a L3 cache interface with on-chip tags to support up to 2MB of off-chip cache. The CPCI-6115 initially supports processor core frequencies of 866 MHz and 1 GHz and an external processor bus speed of 133 MHz.

  • Page 73: Mv64360 Cpu Bus Interface, Mv64360 Ddr Sdram Interface

    4.3.4.2 MV64360 DDR SDRAM Interface The CPCI-6115 supports three banks of DDR SDRAM using 256 megabit, 512 megabit or 1 gigabit DDR SDRAM devices onboard. A 133 MHz (DDR266) operation is used when two or three banks are populated. The SDRAM supports ECC. The SDRAM controller contains four transaction queues - two write buffers and two read buffers.

  • Page 74: Mv64360 32-bit Interface To Devices, Mv64360 Dual Pci/pci-x Interfaces, Mv64360 Integrated Gigabit Ethernet Macs

    The device controller supports up to five banks of devices, of which three are used for Flash Bank A and B, NVRAM/RTC, and serial ports on the CPCI-6115. Each bank supports up to 512 MB of address space, resulting in total device space of 1.5 GB. Each bank has its own parameters register as shown in the following table.

  • Page 75: Mv64360 Integrated 2 Megabit Sram, Mv64360 General-purpose 32-bit Timer/counters, Mv64360 Watchdog Timer

    4.3.4.11 MV64360 I C Interface A two-wire serial interface for the CPCI-6115 board is provided by a master/slave capable I serial controller integrated into the MV64360 device. The I basic functions. The first function is to optionally provide MV64360 register initialization following a reset.

  • Page 76: Interrupt Controller, Pci Bus Arbitration

    MPP pins function as general purpose inputs). Software will configure the MPP pins to function as request/grant pairs for the internal PCI arbiter. The arbitration pairs for the CPCI-6115 are assigned to the MPP pins as shown in the following table.

  • Page 77: Board Reset Logic, Mv64360 Mpp Configuration

    MV64360 internal devices. After reset, all MPP pins default to general purpose inputs. Software must then configure each of the pins for the desired function. The following table defines the function assigned to each MPP pin on the CPCI-6115 board. Table 4-2 MV64360 MPP Pin Function Assignments...

  • Page 78: Mv64360 Reset Configuration

    Partial pin sample on deassertion of reset plus serial ROM initialization via the I user defined initialization. The CPCI-6115 board supports both options. An onboard jumper setting is used to select the option. If the pin sample only method is selected, then states of the various pins on the device AD bus are sampled when reset is deasserted to determine the desired operating modes.

  • Page 79

    Resistor AD[9] Fixed AD[12] Resistor AD[13] Resistor AD[15:14] Resistors AD[16] Resistor AD[17] Fixed CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Default Power-Up Setting Description State of Bit vs. Function SROM Initialization DRAM Pads Calibration SROM Device Address Internal...

  • Page 80

    Resistors AD[25] Fixed AD[28:26] Resistors AD[31:29] TxD0[0] Resistor TxD1[0] Resistor TxD2[0] Resistor CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Default Power-Up Setting Description State of Bit vs. Function DRAM Clock Select DRAM Address/Control Delay DRAM control path pipeline...

  • Page 81: System Memory

    The base memory device is a standard monolithic DDR SDRAM, 8-bits wide, in a 66-pin TSOPII package. The CPCI-6115 can be populated with up to three banks of memory onboard (nine devices per bank). One or two banks can be populated with standard single DDR devices.

  • Page 82: Flash Memory, Nvram, Real-time Clock, Watchdog Timer

    MV64360 when the jumper is installed. There is a boot bank select jumper on the CPCI-6115 that selects either Flash Bank A or Bank B as the boot bank. This jumper effectively routes the MV64360 BOOTCS# pin to either Bank A/Bank B and chip select CS0# to the other bank (Bank B/Bank A).

  • Page 83: Tl16c550c Uart Devices, System Registers, Serial Eeprom Devices, Pci Bus 0.0, Pci Bus 1.0

    4.3.11 PCI Bus 0.0 On the CPCI-6115, PCI Bus 0.0 is connected only to PMC 2 and will support 32/64-bit transfers at 66/133 MHz PCI-X or 33/66 MHz PCI. PCI bus 0.0 is compliant to PCI-X Revision 1.0a and PCI Revision 2.2. VIO is user-selectable between +3.3 V and +5 V by positioning the PMC2 keying pin at the +3.3 V or +5 V site.

  • Page 84: Ide Controller, Intel 21555 Pci-to-pci Bridge, Compactpci Bus, Pmc Slots

    4.3.14 Intel 21555 PCI-to-PCI Bridge The CPCI-6115 uses the Intel 21555 PCI-to-PCI bridge, which is connected to PCI bus 1.0. The 21555 bridge is compliant to PCI Revision 2.2. The following are key features of the 21555: Non-transparent PCI-to-PCI bridge...

  • Page 85

    CompactPCI J5 I/O connector. Both PMC I/O connectors are routed to their respective CompactPCI I/O connector following the PIM differential signalling recommendations. The CPCI-6115 front panel allows for front I/O through the PMC faceplate. PMC slot 1 supports:...

  • Page 86: Miscellaneous, Clock Generation, Interrupt Handling

    These GNTB# pins are routed to the appropriate PCI bus arbiters. M66EN The CPCI-6115 has a weak pull-up on this signal. If this signal is grounded, as it is when a 33 MHz PMC module is installed, it will force the corresponding PCI bus to 33 MHz operation.

  • Page 87: Mv64360 Interrupt Controller

    4.4.2.1 MV64360 Interrupt Controller The CPCI-6115 uses the MV64360 interrupt controller to route internal and external interrupt requests to the CPU and the PCI bus. The MV64360 interrupt controller registers are implemented as part of the CPU interface unit in order to have minimum read latency from CPU interrupt handler.

  • Page 88: Sources Of Reset, Machine Check, Soft Reset, Other Software Considerations

    A hard reset is defined as a reset of all onboard circuitry including the PowerPC hard reset and reset of all onboard peripheral devices. A soft reset is defined as a reset of the PowerPC. The CPCI-6115 has these listed sources of reset: Power-On/undervoltage reset...

  • Page 89: Onboard Power Supplies, Hot Swap Support, Hot Swap Process, Intel 21555 Hot Swap Support

    4.4.3 Onboard Power Supplies The CPCI-6115 CPU board requires +5 V and +3.3 V input power. The +/-12 V input voltages are optional and are routed to the PMC slots. All other required voltages are generated onboard from the +3.3 V or +5 V power. The processor core voltage regulator has a variable output which is set using feedback resistors.

  • Page 90

    Control Register to indicate that the serial preload is complete and the Primary Lockout bit has been cleared, indicating that the card is ready for host initialization. CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Intel 21555 Hot Swap Support...

  • Page 91

    The transition module supports two single-wide (74mm wide by 69mm long) PMC I/O modules. PMC I/O pins 1 through 64 of each PMC slot on the CPCI-6115 SBC are routed from the J3 and J5 connectors to the PMC I/O (PIM1 and PIM2) on the transition module. For a detailed...

  • Page 92

    Transition Module Preparation and Installation Block Diagram The block diagram for the CPCI-6115-MCPTM is shown in the following figure. Figure 5-1 CPCI-6115-MCPTM Block Diagram COM1 RS232 Transceiver 16:8 Mux Compact Flash 1 User I/O J5 Connector CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)

  • Page 93: Preparing The Transition Module

    Two PMC I/O modules (PIM) Four asynchronous serial ports (COM1, COM2, COM3 and COM4) I/O signal multiplexing (IOMUX) CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Transition Module Preparation and Installation Figure 5-2) is used in conjunction with the CPCI-6115...

  • Page 94: Rear Panel Connectors, On-board Connectors And Headers

    Number Serial Ports On-Board Connectors and Headers The following table lists the connectors and headers on the CPCI-6115-MCPTM. Use the links in the Location column to find the connector descriptions and pin assignments or jumper settings. Table 5-2 On-Board Connectors and Headers...

  • Page 95: Ide Compactflash Connector, Pmc I/o Module Connectors

    There are two pairs of 64-pin surface mount connectors on both the standard and MXP version of the CPCI-6115-MCPTM to provide an interface for two optional add-on PMC I/O modules. Each module has an identical PMC I/O connector and a unique Host I/O connector. All serial port signals are at TTL levels.

  • Page 96: Host Io Connectors

    Not Connected Not Connected Not Connected Not Connected Not Connected +5 V Not Connected Not Connected Not Connected CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) PMC I/O Module Connectors +12 V IN1_TXD IN1_DTR IN1_RTS +3.3 V IN2_DCD IN2_RXD...

  • Page 97

    CS3FX1_L DIOR_L +5 V MASTER/SLAVE IORDY DASP PDIAG +5 V Not Connected Not Connected CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Transition Module Preparation and Installation Not Connected Not Connected OUT_DCD Not Connected +3.3 V OUT_RXD OUT_TXD I2C_DATA...

  • Page 98: Pmc I/o Connectors

    PMC IO25 PMC IO27 PMC IO29 PMC IO31 PMC IO33 PMC IO35 PMC IO37 PMC IO39 CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) PMC I/O Module Connectors Not Connected Not Connected OUT_DCD Not Connected +3.3 V OUT_RXD OUT_TXD...

  • Page 99

    I/O signals for the PMC1 I/O, and two 10/100/1000Base-T ethernet ports. The pin assignments for J3 on the processor board and on the CPCI-6115-MCPTM are as follows: (Outer row F is assigned and used as ground pins but is not shown in the table).

  • Page 100

    Connector J5 is a 110 pin AMP Z-pack 2mm hard metric type B connector. This connector routes the I/O signals for the PMC2 I/O signals, the IDE port, four asynchronous serial ports and I2C. The pin assignments for J5 on the processor board and the CPCI-6115-MCPTM are as follows: (Outer row F is assigned and used as ground pins but is not shown in the table).

  • Page 101

    COMn_TD - COMn_RD - Miscellaneous: TMPRSNT_L - TMCOM1_L - MXCLK - MXSYNC_L - MXDI - MXDO - CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Transition Module Preparation and Installation Row B Row C Row D PMC2IO9 PMC2IO8 PMC2IO7 PMC2IO14...

  • Page 102: Basetx Connectors, Com1 And Com2 Connectors (mxp Version)

    I/O module 1. The COM2DIR jumper is a two position (three pin) jumper which controls the origin of the serial port. In one position, COM2 from the CPCI-6115 is enabled. In the other position, the connector is redirected to the PMC I/O module 2.

  • Page 103: Rj-45 To Db-9 Adapter For Com1 To Pc Com1

    A prewired, completely shielded RJ-45 to DB-9 female adapter assembly with 8 position RJ-45 socket on one end to DB-9 socket on the other end is available through Motorola. This can be ordered through Motorola by requesting the following part number: MRJ45DB9ADP-01 (works with either a Motorola or Intel CPU).

  • Page 104: Jumper Settings, Compactflash Jumper, Com1 And Com2 Asynchronous Serial Ports Jumpers

    Jumper Settings This section describes the jumper settings that are required for proper operation prior to installing the CPCI-6115-MCPTM transition module into a chassis backplane. Many boards are already factory configured based on customer requirements, but the jumper settings should be verified before installation.

  • Page 105: Ide Flash, Functional Description

    5.7.1 IDE Flash The CPCI-6115 SBC supports a single IDE channel routed to the J5 User I/O connector. The CPCI-6115-MCPTM contains one 50-pin Type II connector which supports a removable IDE CompactFlash memory card on the primary IDE channel. Refer to the on page 102 for the definition of this connector.

  • Page 106: Ethernet Interface (compactpci Version), Hot-swap Support, Serial Eeprom, Pmc I/o Modules, Asynchronous Serial Ports

    I/O. Two PMC I/O modules are supported on the CPCI-6115-MCPTM, one per PMC site on the CPCI-6115 SBC. The CPCI-6115 SBC maps the PMC user I/O pins onto the CompactPCI J3 and J5 connectors. The CPCI-6115-MCPTM reverses the mapping and brings the signals to a 64-pin EIA-E700 AAAB connector to interface with the PMC I/O module.

  • Page 107: I/o Signal Multiplexing (iomx)

    Asynchronous Serial Ports Due to pin limitations of the J5 connector, the CPCI-6115 SBC multiplexes the serial channel control signals between the CPCI-6115 SBC and the CPCI-6115-MCPTM. This hardware function is transparent to software. The block diagram for the signal multiplexing on the...

  • Page 108

    MXSYNC# is clocked out using the falling edge of MXCLK and MDXO is clocked out with the rising edge of the MXCLK. MXDI is sampled at the rising edge of MXCLK (the CPCI-6115- MCPTM synchronizes MXDI with MXCLK’s rising edge). The timing relationships among...

  • Page 109: Serial Port Redirection, Asynchronous Serial Port Diagrams

    The redirected serial channels are routed to pins reserved on the host I/O connector. A serial port (if any) originating on the PMC located on the CPCI-6115 SBC is connected to the PMC I/O module through the standard 64 bits of PMC user I/O. The PMC I/O module must then loop the serial port back out on its host I/O connector.

  • Page 110: Port Configuration Diagrams, Pmc I/o Module

    CompactPCI J3 and J5 connectors; MCxx905 SBC host I/O, PMC1 I/O and PMC2 I/O. CPCI-6115 SBC host I/O functions are designed into the CPCI-6115 SBC and their presence or absence is determined when that board is built. This I/O cannot be configured at...

  • Page 111: Pmc I/o Module Form Factor

    PMC I/O depends entirely upon which, if any, PMC is installed in one or both of the CPCI-6115 SBC PMC sites. To accommodate the pluggable nature of a PMC, a custom form factor pluggable I/O module is presented here. A physical representation of the CPCI-6115-MCPTM and I/O modules is shown below.

  • Page 112: Pmc I/o Connector, Host I/o Connector, Pmc I/o Module Presence Detection And Identification

    “host I/O module”. This functionality is special to the host (in this case the CPCI-6115 SBC) and so the host I/O module is not a “universal” module. However, if the host I/O connector pinout is reused on future transition modules, the host I/O module may be reused.

  • Page 113: Installing The Pim

    Installing the PIM Procedure If a PIM has already been installed on the CPCI-6115-MCPTM, or you are installing a transition module as it has been shipped from the factory, disregard this section, and proceed to the main installation section titled perform the following steps: 1.

  • Page 114

    PIM front bezel and rear standoffs. Tighten the screws. 8. With the CPCI-6115-MCPTM in the correct vertical position that matches the pin positioning of the backplane, carefully slide the transition module into the appropriate slot and seat tightly into the backplane.

  • Page 115: Installing The Transition Module

    Before touching the product or electronic components, make sure that your are working in an ESD-safe environment. 3. With the CPCI-6115-MCPTM in the correct vertical position that matches the pin positioning of the backplane, carefully slide the transition module into the appropriate slot and seat tightly into the backplane.

  • Page 116: Removing The Transition Module In A Hot-swap Chassis

    Removing the Transition Module in a Hot-Swap Chassis Although the CPCI-6115 SBC can be removed and inserted while power is applied in a hot- swap capable backplane, the CPCI-6115-MCPTMs are not hot-swap capable. Inserting or removing the transition module while the CPU board is active may affect the normal operation of the CPU board.

  • Page 117: Register Description, Overview, Remote Start Via The Pci Bus

    For boards where the 21555 is disabled, the remote start function, as described in the MOTLoad Firmware Package User’s Manual will not work. Applications may also be downloaded to the CPCI-6115 via one of the PCI bus windows provided by the PCI-to-PCI bridge. This method is faster than using the MOTLoad remote interface and may be preferable to use for large downloads.

  • Page 118: Command/response Register Description

    Bit 0 Bits 1 to 7 Bit 8 Bits 9 to 15 Bits 16 to 31 CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Command/Response Register Description Command Options Command Data/Result Description The ownership flag (OWN). A value of 1 indicates the’host’ owns the register.

  • Page 119: Motload Description, Overview, Motload Implementation And Memory Requirements, Motload Firmware

    (for example, DRAM, external cache, flash). Typically, the smallest amount of on-board DRAM that a Motorola SBC has is 32MB. Each supported Motorola product line has its own unique CPCI-6115 CompactPCI Single Board Computer binary image(s).

  • Page 120: Motload Commands, Motload Utility Applications, Motload Tests

    MOTLoad Commands CPCI-6115 CompactPCI Single Board Computer supports two types of commands (applications): utilities and tests. Both types of commands are invoked from the CPCI-6115 CompactPCI Single Board Computer command line in a similar fashion. Beyond that, CPCI- 6115 CompactPCI Single Board Computer utilities and CPCI-6115 CompactPCI Single Board Computer tests are distinctly different.

  • Page 121: Using Motload, Command Line Interface

    Example: CPCI-6115> version Copyright: Motorola Inc.1999-2002, All Rights Reserved MOTLoad RTOS Version 2.0 PAL Version 0.1 (Motorola CPCI-6115) CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) MOTLoad Firmware...

  • Page 122: Command Line Help, Command Line Rules

    There are a few things to remember when entering a MOTLoad command: Multiple commands are permitted on a single command line, provided they are separated by a single semicolon(";"). Spaces separate the various fields on the command line (command/arguments/options). CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Command Line Help...

  • Page 123: Motload Command List

    CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Description One-Line Instruction Assembler Block Compare Byte/Halfword/Word Display Current Board Temperature Block Fill Byte/Halfword/Word Block Copy Block Format...

  • Page 124

    CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Description Checksum Byte/Halfword/Word Display (Show) Device/Node Table Disk Boot (Direct-Access Mass-Storage Device) Down Load S-Record from Host One-Line Instruction Disassembler Echo a Line of Text...

  • Page 125

    CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Description Memory Modify Bytes/Halfwords/Words Execute program from idle processor Display multi-processor control structure Resets board switching master MPU Network Boot (BOOT/TFTP) Display Network Interface Configuration Data...

  • Page 126

    CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Description RAM Bit Toggle RAM Bounce RAM Code Copy and Execute Monitor for ECC Errors RAM March RAM Patterns RAM Permutations RAM Quick...

  • Page 127: Memory Maps, Overview, Default Processor Memory Map

    Memory Maps Overview This chapter supplies information for use of the CPCI-6115 family of Single Board Computers in a system configuration. Here you will find descriptions of the memory maps and software initialization. Memory Maps There are three points of view for memory maps:...

  • Page 128: Processor Memory Map

    256 MB boundary. For example, if memory was 1G on the baseboard and 192 MB on a mezzanine, the beginning of PCI memory would be rounded up to address 0x50000000 (1 GB + 256 MB). CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Size Definition...

  • Page 129: Default Pci Memory Map

    Default PCI Memory Map This is a suggested map only. Motorola developed firmware and software adheres to the following mapping, but end user applications are free to select an alternate mapping. Table 8-2 Suggested PPC Memory Map Processor Address Start...

  • Page 130: Suggested Pci Memory Map

    F100 0000 F10F FFFF F110 0000 F11F FFFF F200 0000 F5FF FFFF FF800 0000 FFFF FFFF CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Size Definition 32 MB Unassigned 32 MB PCI Bus 0 P2P I/O Space 32 MB...

  • Page 131: System I/o Memory Map, Pci Local Bus Memory Map, Compactpci Memory Map

    PCI Local Bus Memory Map There are two PCI local buses on the CPCI-6115: PCI Bus 0.0 and PCI Bus 1.0. The only device on PCI Bus 0.0 is PMC 2. The PCI devices on PCI Bus 1.0 are PMC 1, the CMD 646U2 IDE controller and the Intel 21555 PCI-to-PCI bridge.

  • Page 132: Address Decoding With The 21555, L1, L2 And L3 Cache, System Memory

    8.2.9 L1, L2 and L3 Cache The CPCI-6115 supports the MPC7457 processor on-chip L1 and L2 caches with 2 MB of external L3 cache installed. The CPCI-6115 L3 memory consists of two 8 megabit (256Kx36, 300 MHz, 1.9 ns access) devices providing a total of 2 MB of memory. Data parity checking should be enabled.

  • Page 133: A.1 Embedded Communications Computing Documents, A.2 Manufacturers' Documents

    Related Documentation Embedded Communications Computing Documents The Motorola publications listed below are referenced in this manual, or apply to systems that use this product. You can obtain paper or electronic copies of Embedded Communications Computing publications by: Contacting your local Motorola sales office, or Visiting the Embedded Communications Computing World Wide Web literature site, http://www.motorola.com/computer literature.

  • Page 134: A.3 Related Specifications

    Interface Between Data Terminal Equipment and Data Circuit-Terminating Equipment Employing Serial Binary Data Interchange; Electronic Industries Alliance; http://global.ihs.com/index.cfm CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) (PCI Special Interest Group) (for publications) Related Specifications Publication Number or Search Term...

  • Page 135

    CompactPCI System Management Specification PCI Industrial Manufacturers Group (PICMG) http://www.picmg.com VITA-32-199x Processor PMC Standard for Processor PMC Mezzanine Cards VITA Standards Organization http://www.vita.com/ CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) Related Documentation Publication Number MPR-PPC-RPU-02 Rev. 1.0a 7/24/00 ISBN 1-55860-394-8 PICMG 2.0 R3.0...

  • Page 136

    Related Documentation Related Specifications CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)

  • Page 137

    (Remote Start) firmware as initialization agent hardware configuration hardware management components help command MOTLoad CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) inspecting shipment jumper settings J3 connector (905) pin assignments J5 connector (905) pin assignments jumper settings...

  • Page 138

    J5 connector (TM) J6 header (905) J9 header (905) J99 header (905) power requirements preparation baseboard product, how to order CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) related specifications Remote Start command options field reset sources software OpenHPI specification...

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