Reset Circuit; Clock Circuit; Cl-S6621 - Citizen CL-S6621 Technical Manual

(2) Reset circuit

This circuit performs the system reset.
When power is turned ON, +3.3V increases gradually from 0V. When the voltage at pin 2
(+3.3V) of U6 (Voltage detector) reaches approx. at 2.8 V, nRESET33 signal goes from "Low"
to "High" level after a certain delay time (determined by C7 at pin 5 of U3) has passed.
While nRESET33 signal is "Low", U1A (CPU) and U14 (FPGA) are reset. Also, by nGRESET
signal output from U1A (CPU), U14 (FPGA) and other circuits are reset.
Power ON
+3.3V
0V
H
nRESET33
L

(3) Clock circuit

Crystal oscillator X1 oscillates a 16 MHz clock. This clock is send to U1A (CPU) and the CPU
generates a 128 MHz internal clock and 64 MHz clock.
The 64MHz clock is fed to U14 (FPGA) and U13 (SDRAM)
X2 (Clock generator) oscillates a 48 MHz clock used for optional I/F control.
System Clock
(16MHz)
Clock for optional I/F
(48MHz)
[SA, Main PCB]
+3.3V
Reset
16MHz
X1
C1
C2
X2
+3.3V
Clock Generator
4
V
1
SB
DSC8002DI1(48MHz)
U6
+3.3V
Voltage Detector
2
VDD
OUT
3
CD
VSS
S-1009C28I-M5T1U
[SA, Main PCB]
U1A
CPU
164
X1
R1
165
X2
PCD1 88
R2
3
159
C P10
2
G
2-37
Operation of Control Parts
L : Reset
1
nRESET33
28
5
nGRESET
23
C7
R5
nRESET33
C14
nGRESET
G13
Bus Clock
(64MHz)
R11
BUSCLK
Internal Clock
(128MHz)
U1A
CPU
RESET
U14
FPGA
B3_1
B3_17
nGRESET
U14
FPGA
D15
B3_6
BUSCLK

CL-S6621