Intel PXA27x User Manual page 70

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Section 3.3.1.9 — Synchronous Static Memory Configuration Register (SXCNFG)
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Section 3.3.1.10 — Expansion Memory Timing Configuration
MCMEM0, MCMEM1, MCATT0, MCATT1, MCIO0, MCIO1
The recommended settings for the memory-control registers presume the following:
•
Memory-controller clock frequency (CLK_MEM) = 130 MHz, based upon the value of L in
the Intel
Manager chapter in the Intel
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64MB of SDRAM installed, mapped as 2 devices, 13 row-address bits, 9 column-address bits,
and 16 data bits, one device for the lower and one for the upper data-bus bits.Extended Mode
Register in the SDRAMs set as follows:
-
-
To set these SDRAM characteristics for each device, refer to the following information
sources:
— SDRAM device registers: Infineon HYB/E 25L25610AC 256-MBit Mobile-RAM* data
sheet
— Accessing the SDRAM registers: Intel
SDRAM Mode Register Set Configuration register (see the Memory Controller chapter in
the Intel
It may be necessary to adjust the recommended settings, depending on the following:
•
Desired clock sources — for example, core PLL instead of internal or external processor
oscillator. See the Clocks and Power Manager chapter in the Intel
Developer's Manual.
•
Run- and turbo-mode frequencies (MEM_CLK depends on the core run-mode frequency in
the Intel
Manager chapter in the Intel
•
Use of fast-bus mode (see the Clocks and Power Manager chapter in the Intel
Processor Family Developer's Manual)
•
Expansion-card presence (see
Processor Static Memory Control Register 2 — see the Memory Controller chapter in the
®
Intel
•
Use of SDRAM extended low-power modes — refer to the following information sources:
— SDRAM device registers: Infineon HYB/E 25L25610AC 256-MBit Mobile-RAM* data
sheet
— Accessing the SDRAM registers: Intel
SDRAM Mode Register Set Configuration register (see the Memory Controller chapter in
the Intel
70
®
PXA270 Processor Core Clock Configuration Register. See the Clocks and Power
®
PXA27x Processor Family Developer's Manual.
All SDRAM banks are maintained in self-refresh (all PASR bits clear).
Temperature-compensated refresh (TCR) is set for 45
®
PXA27x Processor Family Developer's Manual)
®
PXA270 Processor Core Clock Configuration Register. See the Clocks and Power
®
PXA27x Processor Family Developer's Manual.)
Section
PXA27x Processor Family Developer's Manual.)
®
PXA27x Processor Family Developer's Manual)
Registers:
o
C.
®
PXA270 Processor Special Low-Power
3.2.1.1) and memory-bus configuration (Intel
®
PXA270 Processor Special Low-Power
®
Intel PXA27x Processor Developer's Kit - User's Guide
®
PXA27x Processor Family
®
PXA27x
®
PXA270