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3.2.1.2
System Configuration Register 2 (SCR2)
The virtual register SCR2, defined in
panel that is used with the kit. This information must be known at boot time in order to properly
configure the processor LCD interface and timing registers.
Note: The SCR is not normally available after the boot sequence has completed. If it is necessary to
access this register at any other time, follow the instructions set out in
Table 17. SCR2 Bit Definitions
Address (see Section 3.2.1):
System configuration word
Bit
15
14
13
GPIO
Name
Reserved
Reset
?
?
?
Bits
Name
15:11
—
10
nGFX_PRES
9:7
AUDIOID
6
ORIENT
5:0
LCDID
† Reset values depend on the display and orientation used.
52
Table
12
11
10
9
103
104
113
AUDIOID
†
†
?
?
Access
Description
—
reserved
Graphics Accelerator Present:
R
0 = Graphics Accelerator is present.
1 = Graphics Accelerator is absent.
Audio CODEC ID
0b000 Reserved
0b001 Philips UCB1400
0b010 AKM AK2440
LCD panel orientation:
R
0 = portrait
1 = landscape
Display panel ID:
0b000001 —
0b000000 —
R
0b000001 —
0b000000 —
all others —
17, contains configuration information for the LCD
®
Intel
SCR2
8
7
6
5
31
30
87
86
ORIENT
†
†
†
†
Toshiba* LTM04C380K VGA, 18-bit, 666 RGB
Toshiba* LTM04C380K VGA, 16-bit, 565 RGB
Toshiba* LTM035A776C VGA, 18-bit, 666 RGB
Toshiba* LTM035A776C VGA, 16-bit, 565 RGB
reserved
®
Intel
PXA27x Processor Developer's Kit - User's Guide
Section
3.2.1.
PXA27x Processor Developer's Kit
4
3
2
1
77
75
74
19
LCDID
†
†
†
†
0
14
†
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