Jtag Interface; Logic-Analyzer Interface; System Configuration Register; Connectors - Intel PXA27x User Manual

2.3.6

JTAG Interface

Two JTAG connectors, the in-circuit emulation (ICE) connector and a stake pin header, provide the
interface for devices on the JTAG chain, such as the main board and Intel
CPLDs, the main board FPGA, and the daughter card. For details of the JTAG interface, see
Section 2.3.9
2.3.7

Logic-Analyzer Interface

Table 7 lists the logic-analyzer connections on the daughter card. For pin assignments, see the
daughter card schematic diagram.
2.3.8

System Configuration Register

Pull-up and pull-down resistors built into the daughter card provide the system with the necessary
configuration information. For details of the System Configuration Register, see
"Virtual Configuration Registers" on page
2.3.9

Connectors

Table 7 lists all of the connectors on the daughter card.
•
For the locations of connectors on the daughter card, see
•
For descriptions of a connector's use, see the referenced section in this document.
•
For pin assignments, see the daughter card schematic diagram.
•
To identify a connector's type, see the daughter card parts list.
Table 7. Connectors, Daughter Card (Sheet 1 of 2)
Designator Name
J1
J2
J3
J4
J5
J8a
J8b
J8c
J9
J12
J13
J14
J15-J19
J20-J21
40
and the daughter card schematic diagram.
Reserved
PXA27x FFUART serial port
13 MHz SMB header
JTAG ICE
32 KHz SMB header
Connector to processor card
Connector to processor card
Connector to processor card
Reserved
RF Test Points
CSSP Bottom Connector
High Speed Logger (HSL) Connector
Logic Analyzer
PMIC Header
50.
Figure
®
Intel PXA27x Processor Developer's Kit - User's Guide
®
PXA270 Processor
Section 3.2.1,
12.