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Bus Clock Control
■
Power sequence control of DC/DCs on board.
■
Interrupts.
■
Data Channel/Fast Mailbox Control.
■
Initialization
The FPGA configuration is performed after an FPGA reset when the configuration is
downloaded from the PROM. The PROM can be updated using a cable and the
Xilinx programming header (JTAG), or from the MPC.
5.1.5.3
XBus External devices
Flash PROM for OpenBoot
The 4-Mbyte flash PROM is used for the OpenBoot and POST firmware.
5.1.6
Intelligent Platform Management Controller
The Renesas H8S/2166 provides the IPM controller (IPMC) function on the Sun
Netra CP3060 blade server. The IPMC provides PICMG 3.0 board management
functionality, and it interfaces to the host CPU through a serial interface. The IPMC
subsystem is powered from the standby power.
The IPMC is responsible for the following:
Dual buffered IPMB interfaces to connect to IPMB-0
■
Serial payload interface to the host through MPC
■
IPMI_L interface to the AMC boards
■
Power control of the entire Sun Netra CP3060 blade server
■
Power and reset control of the AMC board
■
Hot-swap latch input and LED control
■
Power control
■
E-Keying control
■
Environmental monitoring
■
Access to all environmental I
■
Access to all I
■
5-18
Netra CP3060 Board User's Guide • April 2009
2
C devices
2
C devices when MPC is reset
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