Cores And Cache - Sun Microsystems Netra CP3060 User Manual

SPARC
core
DRAM
FIGURE 5-2
5.1.1.2

Cores and Cache

Each of the 8 SPARC cores has support for 4 threads, for a total of 32 threads. This
support consists of a full register file per thread, with most ASI, ASR, and privileged
registers replicated per thread. The 4 threads share the instruction cache, data cache,
and TLBs. Each TLB is 64 entry.
Each core then has 16 Kbytes of primary Instruction Cache (I-cache) and 8 Kbytes of
primary Data Cache (D-cache), each of which is parity protected with redundant
rows and columns for repair.
Lastly there is 3-Mbyte unified L2 cache which is 12-way associative, ECC protected
along with redundant rows and columns. This cache is shared among the 8 internal
cores and is connected through an internal crossbar. The UltraSPARC T1 processor
provides no external cache interface.
SPARC SPARC SPARC SPARC
core core core core
Crossbar
Shared L2 cache
DRAM DRAM
UltraSPARC T1 Multicore Processor Block Diagram
SPARC SPARC SPARC
core core core
DRAM
Chapter 5 Hardware and Functional Descriptions
Multithreaded pipe
Instruction
cache
Integer
pipeline
Data
cache
5-5