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5.1.5
Service Processor MPC885
The Sun Netra CP3060 blade server includes a MPC885 service processor subsystem
used for LDOM configuration and Hypervisor interaction, host system reset, and
boot support. The Sun Netra CP3060 blade server uses the MPC885 to run the vBSC
firmware (on VxWorks). A block diagram of the subsystem is shown in
The following I/O interfaces provided by MPC885 are used by the Sun Netra
CP3060 blade server:
100T – Connects to the Base Fabric switch
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2
I
C – Provides interface to I
■
NVRAM)
UART1 – Provides serial interface to IPMC Payload
■
UART2 – Provides console interface
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5.1.5.1
MPC Bus External Devices
There are three MPC external devices:
SDRAM (64MB) – SDRAM memory for the MPC with ECC.
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Flash – 16-Mbyte flash for the MPC code.
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Disk-On-Chip (64 MB) – Disk-on-Chip (DoC) is used to store FMA logs and
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LDOM configuration
5.1.5.2
Field-Programmable Gate Array
The SSI interface from the UltraSPARC T1 processor connects to a
Field-Programmable Gate Array (FPGA) that provides an internal 32-Kbyte SRAM,
access to external OpenBoot flash PROM through an XBus, and access to the IPMC
and the MPC.
The FPGA serves as a gateway between the UltraSPARC T1 and the MPC subsystem
and provides support functionality for the IPMC. It provides the following
functionality:
32-Kbyte SRAM integrated – used as Mailbox, Data Channel, and scratch pad for
■
POST. The SRAM is accessible both from the UltraSPARC T1 processor through
the SSI interface and from H8 through the H8 bus.
H8 interface providing IPMC support.
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MPC interface.
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SSI Interface (UltraSPARC T1).
■
BUS Interface and Arbiter (Round Robin).
■
2
C devices required by vBSC (DIMM SPDs, TOD,
Chapter 5
Hardware and Functional Descriptions
.
FIGURE 5-1
5-17
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