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FIGURE 5-3
UltraSPARC
5.1.2.2
Memory Subsystem RAS Features
The ECC scheme employed by the UltraSPARC T1 memory controller provides
single-bit correct, double-bit detect ECC protection across the 128 bits of data in each
bank of memory. Also, each DIMM provides an industry-standard 256-byte Serial
Presence Detect (SPD) PROM, of which 128 bytes are available to the system for
dynamic FRU data. Plans are being made to use this 128 bytes for dynamic FRU
data, such as soft error rate information.
The Sun Netra CP3060 blade server also supports the Chip-kill detect ECC scheme,
allowing the detection of up to 4 bits in error, as long as they are not in the same
DRAM. This is made possible by limiting the type of DDR-2 memory DIMMs to only
include x4 organization.
5-8
Netra CP3060 Board User's Guide • April 2009
DDR Memory Diagram
A d d r e s s e s < 1 3 : 0 > , B A < 1 : 0 > , R A S _ L , C A S _ L , W E _ L
CS_L<0>
CS_L<1>
CS_L<2>
T1
n.c.
n.c.
CS_L<3>
128 Data + 16 ECC
35 (DS/DM)
DIMM Pair 0
bank0
bank1
DDR DIMM
DIMM0
72
18
bank0
bank1
DDR DIMM
DIMM1
72
18
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