Vr Power-State Transitions; Svid Address Usage - Intel BX80619I73960X Datasheet

If a power state is not supported by the controller, the slave should acknowledge with
command rejected (11b)
If the VR is in a low power state and receives a SetVID command moving the VID up,
then the VR exits the low power state to normal mode (PS0) to move the voltage up as
fast as possible. The processor must re-issue low power state (PS1, PS2, or PS3)
command if it is in a low current condition at the new higher voltage. See
VR power state transitions.
Figure 7-2.

VR Power-State Transitions

7.1.8.3.6 SVID Voltage Rail Addressing
The processor addresses 4 different voltage rail control segments within VR12 (VCC,
VCCD_01, VCCD_23, and VSA). The SVID data packet contains a 4-bit addressing
code.
Table 7-2.

SVID Address Usage

Notes:
1. Check with VR vendors for determining the physical address assignment method for their controllers.
2. VR addressing is assigned on a per voltage rail basis.
3. Dual VR controllers will have two addresses with the lowest order address, always being the higher phase
count.
4. For future platform flexibility, the VR controller should include an address offset, as shown with +1 not
used.
54
PS1
PWM Address (HEX)
00
01
02
03
04
05
PS0
PS2 PS3
Processor
+1 not used
+1 not used
Electrical Specifications
Figure 7-2 for
V
cc
V
sa
V
CCD_01
V
CCD_23
Datasheet, Volume 1