Low-Power Idle States; Idle Power Management Breakdown Of The Processor Cores; Thread And Core C-State Entry And Exit - Intel BX80619I73960X Datasheet

Power Management
4.2.2

Low-Power Idle States

When the processor is idle, low-power idle states (C-states) are used to save power.
More power savings actions are taken for numerically higher C-states. However, higher
C-states have longer exit and entry latencies. Resolution of C-states occur at the
thread, processor core, and processor package level. Thread level C-states are
available if Hyper-Threading Technology is enabled. Entry and exit of the C-States at
the thread and core level are shown in
Figure 4-1.

Idle Power Management Breakdown of the Processor Cores

Figure 4-2.

Thread and Core C-State Entry and Exit

MWAIT(C1), HLT
C1
While individual threads can request low power C-states, power saving actions only
take place once the core C-state is resolved. Core C-states are automatically resolved
by the processor. For thread and core C-states, a transition to and from C0 is required
before entering any other C-state.
Datasheet, Volume 1
Thread 0 Thread 1
Core 0 State
Processor Package State
MWAIT(C1), HLT
(C1E Enabled)
MWAIT(C3),
P_LVL2 I/O Read
C1E
Figure 4-2.
Thread 0 Thread 1
Core N State
C0
MWAIT(C6),
P_LVL3 I/O Read
C3 C6
MWAIT(C7),
P_LVL4 I/O Read
C7
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