G, S, And C State Combinations; Processor Core / Package Power Management; Enhanced Intel ® Speedstep ® Technology - Intel BX80619I73960X Datasheet

4.1.5

G, S, and C State Combinations

Table 4-6.

G, S, and C State Combinations

Global (G)
State
G0
G0
G0
G0
G1
G1
G2
G3
4.2

Processor Core / Package Power Management

While executing code, Enhanced Intel SpeedStep
processor's frequency and core voltage based on workload. Each frequency and voltage
operating point is defined by ACPI as a P-state. When the processor is not executing
code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, lower
power C-states have longer entry and exit latencies.
4.2.1 Enhanced Intel
The following are the key features of Enhanced Intel SpeedStep
• Multiple frequency and voltage points for optimal performance and power
efficiency. These operating points are known as P-states.
• Frequency selection is software controlled by writing to processor MSRs. The
voltage is optimized based on temperature, leakage, power delivery loadline, and
dynamic capacitance.
— If the target frequency is higher than the current frequency, V
to an optimized voltage. This voltage is signaled by the SVID Bus to the voltage
regulator. Once the voltage is established, the PLL locks on to the target
frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the
target frequency, then transitions to a lower voltage by signaling the target
voltage on the SVID Bus.
— All active processor cores share the same frequency and voltage. In a multi-
core processor, the highest frequency P-state requested amongst all active
cores is selected.
— Software-requested transitions are accepted at any time. The processor has a
new capability from the previous processor generation, it can preempt the
previous transition and complete the new request without waiting for this
request to complete.
• The processor controls voltage ramp rates internally to ensure glitch-free
transitions.
• Because there is low transition latency between P-states, a significant number of
transitions per-second are possible.
30
Processor
Sleep
Core
(S) State
(C) State
S0 C0
S0 C1/C1E
S0 C3
S0 C6/C7
S3 Power off
S4 Power off
S5 Power off
NA Power off
®
SpeedStep
Processor System
State Clocks
Full On On
Auto-Halt On
Deep Sleep On
Deep Power
On
Down
— Off, except RTC
— Off, except RTC
— Off, except RTC
— Power off
®
Technology optimizes the
®
Technology
Power Management
Description
Full On
Auto-Halt
Deep Sleep
Deep Power Down
Suspend to RAM
Suspend to Disk
Soft Off
Hard off
®
Technology:
is ramped up
CC
Datasheet, Volume 1