Power-On Configuration (Poc) Options; Signals With On-Die Termination; Power-On Configuration Option Lands - Intel BX80619I73960X Datasheet

Electrical Specifications
Table 7-5. Signal Groups (Sheet 3 of 3)
Differential/Single
Ended
Power/Other Signals
Notes:
1. Refer to
2. DDR{0/1/2/3} refers to DDR3 Channel 0, DDR3 Channel 1, DDR3 Channel 2, and DDR3 Channel 3.
3. ECC DIMMs are not supported on the processor; thus, these signals are not used.
Table 7-6.

Signals with On-Die Termination

Signal Name
BCLK_SELECT[1:0]
BIST_ENABLE
EAR_N
Notes:
1. Refer to
7.3

Power-On Configuration (POC) Options

Several configuration options can be configured by hardware. The processor samples
its hardware configuration at reset, on the active-to-inactive transition of RESET_N, or
upon assertion of PWRGOOD (inactive-to-active transition). For specifics on these
options, refer to
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset transition of the
latching signal (RESET_N or PWRGOOD).
Table 7-7.

Power-On Configuration Option Lands

BCLK input select
Execute BIST (Built-In Self Test)
Power-up Sequence Halt for ITP configuration
Notes:
1. BIST_ENABLE is sampled at RESET_N de-assertion.
2. This signal is sampled at PWRGOOD assertion.
Datasheet, Volume 1
Buffer Type
Power / Ground
Sense Points
Chapter 6, "Signal Descriptions,"
Pull Up /Pull
Down
Pull up
Pull Up
Pull Up
Table 7-16 for details on the R
Table 7-7.
Configuration Option
VCC, VTTA, VTTD, VCCD_01, VCCD_23,VCCPLL, VSA
and VSS
VCC_SENSE
VSS_VCC_SENSE
VSS_VTTD_SENSE
VTTD_SENSE
VSA_SENSE
VSS_VSA_SENSE
for signal description details.
Rail
VTT
VTT
VTT
(Buffer on Resistance) value for this signal.
ON
Land Name
BCLK_SELECT[1:0]
BIST_ENABLE
EAR_N
1
Signals
Value Units Notes
2K Ohm
2K Ohm
2K Ohm
Notes
1
2
1
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