Package C2 State; Package C3 State; Package C6 State - Intel BX80619I73960X Datasheet

The package enters the C1E state when:
• All cores have directly requested C1E using MWAIT(C1) with a C1E sub-state hint
• All cores are in a power state lower that C1/C1E but the package low power state is
limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR
• All cores have requested C1 using HLT or MWAIT(C1) and C1E auto-promotion is
enabled in IA32_MISC_ENABLES
No notification to the system occurs upon entry to C1/C1E.
4.2.5.3

Package C2 State

The Package C2 state is an intermediate state that represents the point at which the
system level coordination is in progress. The package cannot reach this state unless all
cores are in at least C3.
The package will remain in C2 when:
• it is awaiting for a coordinated response
• the coordinated exit latency requirements are too stringent for the package to take
any power saving actions
If the exit latency requirements are high enough, the package will transition to C3 or
C6 depending on the state of the cores.
4.2.5.4

Package C3 State

A processor enters the package C3 low power state when:
• At least one core is in the C3 state
• The other cores are in a C3 or lower power state, and the processor has been
granted permission by the platform
• L3 shared cache retains context and becomes inaccessible in this state
• Additional power savings actions, as allowed by the exit latency requirements,
include putting PCIe* links in L1, the uncore is not available, further voltage
reduction can be taken
• In package C3, the ring will be off and as a result no accesses to the LLC are
possible. The content of the LLC is preserved
4.2.5.5

Package C6 State

A processor enters the package C6 low power state when:
• At least one core is in the C6 state
• The other cores are in a C6 or lower power state, and the processor has been
granted permission by the platform
• L3 shared cache retains context and becomes inaccessible in this state
• Additional power savings actions, as allowed by the exit latency requirements,
include putting PCIe* links in L1, the uncore is not available, further voltage
reduction can be taken
In package C6 state, all cores have saved their architectural state and have had their
core voltages reduced to zero volts. The LLC retains context, but no accesses can be
made to the LLC in this state, the cores must break out to the internal state package C2
for snoops to occur.
36
Power Management
Datasheet, Volume 1