Direct Media Interface Gen 2 (Dmi2); Platform Environment Control Interface (Peci); Power Management Support; Processor Package And Core States - Intel BX80619I73960X Datasheet

Introduction
1.2.3

Direct Media Interface Gen 2 (DMI2)

• Serves as the chip-to-chip interface to the PCH
• The DMI2 port supports x4 link width and only operates in a x4 mode when in DMI2
• Operates at PCIe2 or PCIe1 speeds
• Transparent to software
• Processor and peer-to-peer writes and reads with 64-bit address support
• APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined "End of
Interrupt" broadcast message when initiated by the processor.
• System Management Interrupt (SMI), SCI, and SERR error indication
• Static lane numbering reversal support
• Supports DMI2 virtual channels VC0, VC1, VCm, and VCp
1.2.4

Platform Environment Control Interface (PECI)

The PECI is a one-wire interface that provides a communication channel between a
PECI client (the processor) and a PECI master (the PCH). Refer to the processor
Thermal Mechanical Specification and Design Guide (see
Documents") for additional details on PECI services available in the processor.
• Supports operation at up to 2 Mbps data transfers
• Link layer improvements to support additional services and higher efficiency over
PECI 2.0 generation
• Services include processor thermal and estimated power information, control
functions for power limiting, P-state and T-state control, and access for Machine
Check Architecture registers and PCI configuration space (both within the processor
package and downstream devices)
• Single domain (Domain 0) is supported
1.3

Power Management Support

1.3.1

Processor Package and Core States

• ACPI C-states as implemented by the following processor C-states
— Package: PC0, PC1/PC1E, PC2, PC3, PC6 (Package C7 is not supported)
— Core: CC0, CC1, CC1E, CC3, CC6, CC7
• Enhanced Intel SpeedStep
1.3.2

System States Support

• S0, S1, S3, S4, S5
1.3.3

Memory Controller

• Multiple CKE power down modes
• Multiple self-refresh modes
• Memory thermal monitoring using MEM_HOT_C01_N and MEM_HOT_C23_N Signals
1.3.4

PCI Express*

• L0s and L1 ASPM power management capability
Datasheet, Volume 1
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Technology
Section 1.7, "Related
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