Jtag And Tap Signals; Serial Vid Interface (Svid) Signals; Svid Signals - Intel BX80619I73960X Datasheet

Signal Descriptions
6.6

JTAG and TAP Signals

Table 6-10. JTAG and TAP Signals
Signal Name
BPM_N[7:0]
PRDY_N
PREQ_N
TRST_N
6.7

Serial VID Interface (SVID) Signals

Table 6-11. SVID Signals
Signal Name
SVIDALERT_N
SVIDCLK
SVIDDATA
Datasheet, Volume 1
Breakpoint and Performance Monitor Signals: I/O signals from the processor
that indicate the status of breakpoints and programmable counters used for
monitoring processor performance. These are 100 MHz signals.
External Alignment of Reset, used to bring the processor up into a deterministic
EAR_N
state. This signal is pulled up on the die; refer to
Probe Mode Ready is a processor output used by debug tools to determine
processor debug readiness.
Probe Mode Request is used by debug tools to request debug operation of the
processor.
TCK (Test Clock) provides the clock input for the processor Test Bus (also
TCK
known as the Test Access Port).
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
TDI
serial input needed for JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the processor. TDO
TDO
provides the serial output needed for JTAG specification support.
TMS (Test Mode Select) is a JTAG specification support signal used by debug
TMS
tools.
TRST_N (Test Reset) resets the Test Access Port (TAP) logic. TRST_N must be
driven low during power on Reset.
Serial VID alert.
Serial VID clock.
Serial VID data out.
Description
Table 7-6 for details.
Description
45