Reserved Or Unused Signals; Signal Group Summary; Signal Description Buffer Types - Intel BX80619I73960X Datasheet

7.1.9

Reserved or Unused Signals

All Reserved (RSVD) signals must not be connected. Connection of these signals to V
V , V
TTA TTD
component malfunction or incompatibility with future processors. See
"Processor Land Listing,"
Reserved signals.
For reliable operation, always connect unused inputs or bi-directional signals to an
appropriate signal level. Unused active high inputs should be connected through a
resistor to ground (V
interfere with some Test Access Port (TAP) functions, complicate debug probing, and
prevent boundary scan testing. A resistor must be used when tying bi-directional
signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability.
7.2

Signal Group Summary

Signals are grouped by buffer type and similar characteristics as listed in
buffer type indicates which signaling technology and specifications apply to the signals.
Table 7-4.

Signal Description Buffer Types

Signal
Analog
Asynchronous
CMOS
DDR3
DMI2
Open Drain CMOS
PCI Express*
Reference
SSTL
Notes:
1. Qualifier for a buffer type.
56
, V V , V , or to any other signal (including each other) can result in
CCD, CCPLL SS
for a land listing of the processor and the location of all
). Unused outputs maybe left unconnected; however, this may
SS
Analog reference or output. May be used as a threshold voltage or for buffer
compensation
1
Signal has no timing relationship with any system reference clock.
CMOS buffers: 1.05 V or 1.5 V tolerant
DDR3 buffers: 1.5 V tolerant
Direct Media Interface Gen 2 signals. These signals are compatible with PCI Express*
2.0 and 1.0 Signaling Environment AC Specifications.
Open Drain CMOS (ODCMOS) buffers: 1.05 V tolerant
PCI Express* interface signals. These signals are compatible with PCI Express*
Signalling Environment AC Specifications and are AC coupled. The buffers are not
3.3-V tolerant. Refer to the PCIe specification.
Voltage reference signal.
Source Series Terminated Logic. (JEDEC SSTL_15)
Electrical Specifications
Chapter 8,
Description
,
CC
Table 7-4. The
Datasheet, Volume 1