Interfaces; System Memory Support; Pci Express - Intel BX80619I73960X Datasheet

Introduction
1.2

Interfaces

1.2.1

System Memory Support

• The processor supports 4 DDR3 channels with 1 unbuffered DIMM per channel
• Unbuffered DDR3 DIMMs supported
• Data burst length of eight cycles for all memory organization modes
• Memory DDR3 data transfer rates of 1066, 1333, and 1600 MT/s
• DDR3 UDIMM standard I/O Voltage of 1.5 V
• 1-Gb, 2-Gb, and 4-Gb DDR3 DRAM technologies supported for these devices:
— UDIMMs x8, x16
• Up to 2 ranks supported per memory channel, 1 or 2 ranks per DIMM
• Open with adaptive idle page close timer or closed page policy
• Command launch modes of 1n/2n
• Improved Thermal Throttling with dynamic CLTT
• Memory thermal monitoring support for DIMM temperature using two memory
signals, MEM_HOT
1.2.2

PCI Express*

• Support for PCI Express* 2.0 (5.0 GT/s), PCI Express* (2.5 GT/s), and capable of
up to PCI Express* 8.0 GT/s.
• Up to 40 lanes of PCI Express* interconnect for general purpose PCI Express
devices capable of up to 8.0 GT/s speeds that are configurable for up to 10
independent ports.
• Negotiating down to narrower widths is supported, see
— x16 port (Port 2 & Port 3) may negotiate down to x8, x4, x2, or x1
— x8 port (Port 1) may negotiate down to x4, x2, or x1
— x4 port (Port 0) may negotiate down to x2, or x1
— When negotiating down to narrower widths, there are caveats as to how lane
reversal is supported
• Address Translation Services (ATS) 1.0 support
• Hierarchical PCI-compliant configuration mechanism for downstream devices
• Traditional PCI style traffic (asynchronous snooped, PCI ordering)
• PCI Express* extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
• PCI Express* Enhanced Access Mechanism. Accessing the device configuration
space in a flat memory mapped fashion.
Datasheet, Volume 1
Figure 1-2
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