Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet page 65

Intel itanium processor quad-core 1.86-1.73 ghz with 24 mb l3 cache 9350, intel itanium processor quad-core 1.73-1.60 ghz with 20 mb l3 cache 9340, intel itanium processor quad-core 1.60-1.46 ghz with 20 mb l3 cache 9330, intel itanium processor quad-core
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Electrical Specifications
VROUTPUT_ENABLE0 signal. After VROUTPUT_ENABLE0 is asserted the sequence of
powering up the VCCUNCORE and VCCCORE supplies and the VCCCACHE (Intel
®
Itanium
For the Intel
VCCCACHE supplies power the sysint, cores and large cache arrays respectively.
For the Intel
supplies power the sysint, the cores and the large cache arrays respectively.
When all supplies are up and stable, Ararat asserts VRPWRGD which signals the
external environment that it can assert the PWRGOOD signal. PWRGOOD assertion
initiates the processor internal cold reset sequence.
With reference to the power sequencing timing requirements imposed by the Ararat VR
as shown in
taken for an Ararat regulator to bring up each of its output voltages can be found in the
Ararat 170 Watt Voltage Regulator Module Design Guide for the Intel
Processor 9300 Series and the Ararat II Voltage Regulator Module Design Guide for the
®
Intel
Itanium
When the platform asserts PWRGOOD to the processor, the Intel® Itanium® Processor
9300 Series requires a minimum of 10 ms to complete its internal reset sequence
before deasserting RESET_N, while the Intel® Itanium® Processor 9500 Series
requires a minimum of 15 ms. For platforms that use both processors, a minimum of
15 ms is needed to meet the requirements of both processors.
During platform initialization, the RESET_N pin to any component in the platform can
be removed ONLY after all other components have had sufficient time to sample their
respective reset pins. This is needed to prevent unknown behavior that may result if
any one system component comes out of reset before other components have received
the reset signal.
With the exception of standby miscellaneous pins, all input pins, bi-directional pins, and
terminated output pins must not be allowed to exceed the processor's actual VCCIO
voltage prior to and during ramp up of the VCCIO supply.
®
®
Intel
Itanium
Processor 9300 Series and 9500 Series Datasheet
Processor 9300 Series) begins.
®
®
Itanium
Processor 9300 Series, the VCCUNCORE, VCCCORE and
®
®
Itanium
Processor 9500 Series, the VCCUNCORE and VCCCORE
Figure 2-17
and
Figure
®
Processor 9500 Series.
2-18, timing specifications for the elapsed time
®
®
®
Itanium
65

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