(Intel ® Itanium ® Processor 9300 Series) - Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet

Table 7-1. Signal Definitions for the Intel
Itanium
Name
FBD1NBI[C/D][P/N][12:0]
FBD1NBI[C/D][P/N][13]
FBD0SBO[A/B][P/N][9:0]
FBD0SBO[A/B][P/N][10]
FBD1SBO[C/D][P/N][9:0]
FBD1SBO[C/D][P/N][10]
FLASHROM_CFG[2:0]
FLASHROM_CLK
FLASHROM_CS[3:0]_N
FLASHROM_DATI
FLASHROM_DATO
FLASHROM_WP_N
162
®
9500 Series (Sheet 4 of 8)
Type
I These differential pair data signals generated from the branch one, channel C and D
of FB-DIMMs are input to the processor.
FB-
DIMM
Interface
Name
Example: FBD1NBICP[0] represents FB-DIMM branch 1, northbound data input lane
0 signal of channel C and positive bit of the differential pair.
I These signals are spare lanes, and are intended for Reliability, Availability, and
Serviceability (RAS) coverage on the Intel
signals are not used by Intel
O These differential pair output data signals generated from the processor to the
branch zero, channel A and B of FB-DIMMs.
FB-
DIMM
Interface
Name
Example: FBD0SBOAP[0] represents FB-DIMM branch 1, southbound data output
lane 0 signal of channel A and positive bit of the differential pair.
O These signals are spare lanes, and are intended for Reliability, Availability, and
Serviceability (RAS) coverage on the Intel
signals are not used by Intel
O These differential pair output data signals generated from the processor to the
branch one, channel C and D of FB-DIMMs.
FB-
DIMM
Interface
Name
Example: FBD1SBOCP[0] represents FB-DIMM branch 1, southbound data output
lane 0 signal of channel C and positive bit of the differential pair.
O These signals are spare lanes, and are intended for Reliability, Availability, and
Serviceability (RAS) coverage on the Intel
signals are not used by Intel
I These are input signals to the processor that would initialize and map the Flash
ROM upon reset. After reset is deasserted this input would be ignored by the
processor logic. These pins are sampled during all resets except warm-logic reset.
O The Flash ROM clock.
O Flash ROM chip selects. Up to four separate flash ROM parts may be used.
I Serial Data Input (from ROM(s) to processor).
O Serial Data Output (from processor to ROM(s))
O Flash ROM write-protect.
® Itanium ® Processor 9300 Series and Intel
Description
1 NB I
Branch North Input
Number Bound
®
Itanium
® ®
Itanium 9300 Processor Series.
0 SB O
Branch South Output
Number Bound
®
Itanium
® Itanium ® 9300 Processor Series.
1 NB O
Branch North Output
Number Bound
®
Itanium
® ®
Itanium 9300 Processor Series.
® ®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Signal Definitions
C/D P/N [12:0]
Channel Differential Lane
Pair Number
Polarity
Positive/
Negative
®
9500 Processor Series. These
A/B P/N [9:0]
Channel Differential Lane
Pair Number
Polarity
Positive/
Negative
®
9500 Processor Series. These
C/D P/N [9:0]
Channel Differential Lane
Pair Number
Polarity
Positive/
Negative
®
9500 Processor Series. These
®