Signal Definitions; Signal Definitions For The Intel - Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet

Signal Definitions

7
Signal Definitions
This Chapter provides an alphabetical listing of all Intel
Series and Intel
directions (Input, Output, I/O) and signal descriptions.
For a complete pinout listing including processor specific pins, please refer to
Chapter 3, "Pin
Table 7-1.

Signal Definitions for the Intel

Itanium
Name
BOOTMODE[1:0]
CPU_PRES[A|B]_N
CPU_PRES[1:4]_N
CSI[5:0]R[P/N]CLK
CSI[5:0]T[P/N]CLK
® ®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
® ®
Itanium Processor 9500 Series signals. The tables list the signal
Listing".
®
9500 Series (Sheet 1 of 8)
Type
I The BOOTMODE[1:0] inputs specify which way the Intel
Series and Intel
modes, refer to the Intel
Specification or the Intel
Specification. To pull any of these inputs high, they should be strapped to VCCIO
through a pull-up resistor, and to pull these low, they should be strapped to GND.
These pins are sampled during all resets except warm-logic reset.
I/O CPU Present pads. These pins at the top of the package are part of a daisy chain
that indicates to the platform that the processor and Ararat are properly installed
into the socket.
I/O CPU Present Pads. These pads at the bottom of the package are part of a daisy
chain that indicates to the platform that the processor and Ararat are properly
installed into the socket. Motherboard routing guidelines for these pins are
documented in the Intel
Processor 9500 Series Platform Design Guide.
I The receive clock signals are inputs to the Intel
®
and Intel Itanium
both ends but may differ by a fixed phase. An Intel
receiver port receives a forwarded clock from the transmitter side of the remote
port and vice-versa, to maintain timing reference at either end of the link.
Intel
QuickPath
Interconnect
Interface Name
Example: CSI4RPCLK represents port 5 clock receive signal and positive bit of the
differential pair.
O These transmit clock signals are driven by the processor and are required to be the
same frequency at both ends but may differ by a fixed phase. An Intel
Interconnect local port transmit side sends a forwarded clock to the receive side of
the remote port and vice-versa, to maintain timing reference at either end of the
link.
Intel
QuickPath
Interconnect
Interface Name
Example: CSI4TPCLK represents port 5 clock transmit signal and positive bit of the
differential pair.
® ®
Itanium Processor 9300 Series and Intel
Description
® ®
Itanium Processor 9500 Series will boot. For details on the
® Itanium ® Processor 9300 Series External Design
® Itanium ® Processor 9500 Series External Design
® ®
Itanium 9300 Series Processor and Intel
®
9500 Series and are required to be the same frequency at
®
5:0 R
Port Receiver
Number
®
5:0 T
Port Number Transmitter
® ®
Itanium Processor 9300
® ®
Itanium Processor 9300
®
Itanium
® ®
Itanium Processor 9300 Series
® QuickPath Interconnect local
P/N CLK0
Differential Pair Clock0
Polarity
Positive/
Negative
®
QuickPath
P/N CLK0
Differential Clock0
Pair
Polarity
Positive/
Negative
®
®
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