Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet page 27

Electrical Specifications
Table 2-3. Intel ® QuickPath Interconnect/Intel
Reference Clock Specifications (Sheet 2 of 2)
Symbol
T Allowed time before ringback
Stable
Accumulated rms jitter over n UI of a
given PLL model output in response to
the jittery reference clock input. The
T
- - -
PLL output is generated by convolving
REFCLK JITTER RMS
ONEPLL the measured reference clock phase
jitter with a given PLL transfer
function. Here n=12.
Note:
1. Measurement taken from single-ended waveform.
2. The given PLL parameters are: Underdamping (z) = 0.8 and natural frequency = fn = 7.86E6 Hz; wn = 2 *fn. N_minUI = 12
®
for Intel QuickPath Interconnect 4.8 Gt/s channel.
3. Measurement taken from differential waveform.
4. Measured from -150 mV to +150 mV on the differential waveform (derived from SYSCLK minus SYSCLK_N). The signal must
be monotonic through the measurement region for rise and fall time. The 300 mV measurement window is centered on the
differential zero crossing. See
5. Measured at crossing point where the instantaneous voltage value of the rising edge SYSCLK equals the falling edge
SYSCLK_N. See Figure 2-2.
6. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all
crossing points for this measurement. See
7. Defined as the total variation of all crossing voltages of Rising SYSCLK and falling SYSCLK_N. This is the maximum allowed
variance in Vcross for any particular system. See
8. Defined as the maximum instantaneous voltage including overshoot. See
9. Defined as the minimum instantaneous voltage including undershoot. See
10. T is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges
Stable
before it is allowed to droop back into the VRB ±100 mV range. See
Figure 2-2. Single-ended Maximum and Minimum Levels and V
Figure 2-3. V
cross-delta
® ®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Parameter
Figure 2-4.
Figure 2-3.
Figure 2-2.
Definition
® Scalable Memory Interconnect
Min Nom Max
500
0.5
Figure 2-2.
Figure 2-2.
Figure 2-5.
cross
Units Notes
ps 3, 10
ps 2
Levels
27