Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet page 163

Signal Definitions
Table 7-1. Signal Definitions for the Intel
Itanium
Name
FORCEPR_N
LRGSCLSYS
MEM_THROTTLE_L
PIR_SCL
PIR_SDA
PIR_A0, PIR_A1
SM_WP
PRBMODE_REQ_N
PRBMODE_RDY_N
PROCHOT_N
PROCTYPE
PWRGOOD
RESET_N
RSVD
SKTID[2:0]
SMBCLK
SMBDAT
® ®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
®
9500 Series (Sheet 5 of 8)
Type
I When logic 0, forces processor power reduction.
Refer to the Intel
9500 Series Platform Design Guide for a detailed signal description.
I The header mode is selected by the LRGSCLSYS strapping pin value sampled only
during COLD reset. LRGSCLSYS, when tied to VCCIO using a 50 ohm resistor, puts
the processor in extended header mode, and LRGSCLSYS, when tied to GND, puts
the processor in standard header mode.
I When this pin is asserted on the Intel
internal memory controllers throttle the memory command issue rate to a
configurable fraction of the nominal command rate settings. This pin is not used on
the Intel ® Itanium
I (Processor Information ROM Serial Clock): The PIR_SCL input clock is used to clock
data into and out of the on package PIROM device. This signal applies to the
EEPROM, which is composed of the PIROM and the OEM Scratch PAD.
I/O (Processor Information ROM Serial Data): The PIR_SDA pin is a bidirectional signal
for serial data transfer. This signal applies to the EEPROM, which is composed of the
PIROM and the OEM Scratch PAD.
I (Processor Information ROM Address[0:1]): The PIR_A[0:1] pins are used as the
PIROM memory address selection signals. This bus applies to the EEPROM, which is
composed of the PIROM and the OEM Scratch PAD.
I WP (Write Protect) can be used to write protect the Scratch EEPROM. The Scratch
EEPROM is write-protected when this input is pulled high to VCC33_SM.
I Input from Extended Debug Port (XDP) to make a probe mode request.
O Output to XDP to acknowledge probe mode request.
O The assertion of PROCHOT_N (processor hot) indicates that the processor die
temperature has reached its thermal limit.
O PROCTYPE output informs the platform the processor type. PROCTYPE is tied to VSS
internally to indicate the Intel
internally to indicate the Intel
require a platform pull-up or pull-down.
I The processor requires this signal to be a clean indication that all the processor
clocks and power supplies are stable and within their specifications. "Clean" implies
that the signal will remain low (capable of sinking leakage current), without
glitches, from the time that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high state.
PWRGOOD can be driven inactive at any time, but clocks and power must again be
stable before a subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor. This signal is used to
protect internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
I Asserting the RESET_N signal resets the processor to a known state and invalidates
its internal caches without writing back any of their contents. BOOTMODE[0:1]
signals are sampled during all RESET_N assertions for selecting appropriate
BOOTMODE.
These pins are reserved and must be left unconnected.
I Socket ID strapping pins. To pull any of these inputs high, they should be strapped
to VCCIO, and to pull them low, they should be strapped to VSS. SKTID[2:0]
partially determine the node address.
I The SMBus Clock (SMBCLK) signal is an input clock to the system management
logic which is required for operation of the system management features of the
Intel ® Itanium
processors. This clock is driven by the SMBus controller and is asynchronous to
other clocks in the processor. This is an open drain signal. Intel
Processor 9300 Series and Intel
I/O The SMBus Data (SMBDAT) signal is the data signal for the SMBus. This signal
provides the single-bit mechanism for transferring data between SMBus devices.
This is an open drain signal. Intel
Itanium ® 9500 Series are Slave only.
® Itanium ® Processor 9300 Series and Intel
Description
® Itanium ® 9300 Series Processor and Intel
®
Itanium
® 9500 Processor Series.
® ®
Itanium 9300 Processor Series and VCC33_SM
® Itanium ® 9500 Processor Series. This pin does not
® Processor 9300 Series and Intel
® ®
Itanium 9500 Series are Slave only.
® Itanium ®
® Itanium ® Processor
®
Processor 9300 Series, the
® Itanium ® 9500 Series
® ®
Itanium
Processor 9300 Series and Intel
®
®
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