Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet page 34

Intel itanium processor quad-core 1.86-1.73 ghz with 24 mb l3 cache 9350, intel itanium processor quad-core 1.73-1.60 ghz with 20 mb l3 cache 9340, intel itanium processor quad-core 1.60-1.46 ghz with 20 mb l3 cache 9330, intel itanium processor quad-core
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Table 2-8.
Intel
®
Itanium
(Sheet 2 of 2)
Symbol
Z
TX_LINK_DETECT
V
TX_LINK_DETECT
T
DATA_TERM_SKEW
T
INBAND_RESET_
SENSE
Tclk
_DET
T
CLK_FREQ_DET
T
Refclk-Tx-Variability
T
Refclk-Rx-Variability
L
D+/D-RX-Skew
BER
Lane
Notes:
1. Used during initialization. It is the state of "OFF" condition for the receiver when only the minimum termination
is connected.
®
Table 2-9.
Intel
Itanium
Values for Intel
Symbol
V
Tx-diff-pp-pin
Z
TX_LOW_CM_DC
Z
RX_LOW_CM_DC
V
Tx-cm-dc-pin
V
Tx-cm-ac-pin
TX
duty-pin
TX
jitUI-UI-1E-7-pin
TX
jitUI-UI-1E-9-pin
34
®
Processor 9500 Series Link Speed Independent Specifications
Parameter
Link Detection Resistor
500
Link Detection Resistor
Pull-up Voltage
Skew between first to last
data termination meeting
Z
RX_LOW_CM_DC
Time taken by inband
reset detector to sense
Inband Reset
Time taken by clock
detector to observe clock
stability
Time taken by clock
frequency detector to
decide slow vs.
operational clock after
stable clock
Phase variability between
reference Clk (at Tx
input) and Tx output.
Phase variability between
1000
reference Clk (at Rx
input) and Rx output.
Phase skew between D+
and D- lines for any data
bit at Rx
Bit Error Rate per lane
valid for 4.8 and 6.4 GT/s
®
Processor 9500 Series Transmitter and Receiver Parameter
®
QPI Channel at 4.8 GT/s (Sheet 1 of 2)
Parameter
Transmitter differential swing
DC resistance of Tx terminations
at half the single ended swing
(which is usually 0.25*V
Tx-diff-pp-
) bias point
pin
DC resistance of Rx terminations
at half the single ended swing
(which is usually 0.25*V
Tx-diff-pp-
) bias point
pin
Transmitter output DC common
mode, defined as average of V
and V
D-
Transmitter output AC common
mode, defined as ((V
+ V
D+
V
)
Tx-cm-dc-pin
Average of UI-UI jitter
UI-UI jitter measured at Tx output
pins with 1E-7 probability
UI-UI jitter measured at Tx output
pins with 1E-9 probability.
®
Intel
Min
Nom
Max
2000
max VCCIO
128
1.5
20K
32
500
0.03
1.0E-14
Min
Nom
900
1400
37.4
50
37.4
50
0.23
0.27
D+
-0.0375
0.0375
)/2 -
D-
-0.055
0.055
-0.075
0.075
-0.085
0.085
®
Itanium
Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
Unit
Notes
Ω
V
UI
μs
UI
Reference
Clock Cycles
psec
psec
UI
Events
Max
Unit
Notes
mV
1
Ω
Ω
Fraction of
V
Tx-diff-pp-pin
Fraction of
2
V
Tx-diff-pp-pin
UI
UI
UI

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