Intel® Xeon® Processor 5600 Series Specification Update, March - Intel Xeon 5600 Series Specification Update

Table 3. Errata Summary Table (Sheet 2 of 4)
Steppings
Errata
Number
B-1
BD25 X
BD26 X
BD27 X
BD28 X
BD29 X
BD30 X
BD31 X
BD32 X
BD33 X
BD34 X
BD35 X
BD36 X
BD37 X
BD38 X
BD39 X
BD40 X
BD41 X
BD42 X
BD43 X
BD44 X
BD45 X
BD46 X
BD47 X
BD48 X
BD49 X
BD50 X
BD51 X
Intel® Xeon® Processor 5600 Series
Specification Update, March 2010
Status
Intel® QuickPath Memory Controller May Hang Due to Uncorrectable ECC Errors
No Fix
Occurring on Both Channels in Mirror Channel Mode
Simultaneous Correctable ECC Errors on Different Memory Channels With Patrol
No Fix
Scrubbing Enabled May Result in Incorrect Information Being Logged
The Memory Controller tTHROT_OPREF Timings May be Violated During Self
No Fix
Refresh Entry
Synchronous Reset of IA32_APERF/IA32_MPERF Counters on Overflow Does Not
No Fix
Work
Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in
No Fix
Stuck Core Operating Ratio
Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an
No Fix
Unexpected Interrupt
No FIx Faulting MMX Instruction May Incorrectly Update x87 FPU Tag Word
xAPIC Timer May Decrement Too Quickly Following an Automatic Reload While in
No Fix
Periodic Mode
Reported Memory Type May Not Be Used to Access the VMCS and Referenced
No Fix
Data Structures
No Fix B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set
No Fix Core C6 May Clear Previously Logged TLB Errors
Changing the Memory Type for an In-Use Page Translation May Lead to Memory-
No Fix
Ordering Violations
No Fix A String Instruction that Re-maps a Page May Encounter an Unexpected Page Fault
Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode Interrupt is
No Fix
Received while All Cores in C6
No Fix Two xAPIC Timer Event Interrupts May Unexpectedly Occur
EOI Transaction May Not be Sent if Software Enters Core C6 During an Interrupt
No Fix
Service Routine
No Fix FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM
No Fix APIC Error "Received Illegal Vector" May be Lost
DR6 May Contain Incorrect Information When the First Instruction After a MOV SS,r/
No Fix
m or POP SS is a Store
An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a
No Fix
System Hang
No Fix IA32_PERF_GLOBAL_CTRL MSR May be Incorrectly Initialized
No Fix ECC Errors Can Not be Injected on Back-to-Back Writes
Performance Monitor Counter INST_RETIRED.STORES May Count Higher than
No Fix
Expected
Sleeping Cores May Not be Woken Up on Logical Cluster Mode Broadcast IPI Using
No Fix
Destination Field Instead of Shorthand
No Fix Faulting Executions of FXRSTOR May Update State Inconsistently
Failing DIMM ID May be Incorrect in the 2DPC Configuration When Mirroring is
No Fix
Enabled
No Fix ISSUEONCE Bit in MC_SCRUB_CONTROL Register Does Not Work Correctly
ERRATA
15