Fsb Clock (Bclk[1:0]) And Processor Clocking; Voltage Identification; Core Frequency To Fsb Multiplier Configuration; Datasheet - Intel SL8J6 - Pentium 4 Processor Datasheet

Electrical Specifications
2.2.3

FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor.
As in previous generation processors, the processor core frequency is a multiple of the BCLK[1:0]
frequency. No user intervention is necessary, and the processor will automatically run at the speed
indicated on the package. The processor uses a differential clocking implementation.
Table 2.

Core Frequency to FSB Multiplier Configuration

Multiplication of System
Core Frequency to FSB
Frequency
NOTES:
1. Individual processors operate only at or below the rated frequency.
2.3

Voltage Identification

The VID specification for the processor is supported by the Voltage Regulator-Down (VRD) 10.0
Design Guidelines for Desktop Socket 478. The voltage set by the VID pins is the maximum
voltage allowed by the processor. A minimum voltage is provided in
frequency. This allows processors running at a higher frequency to have a relaxed minimum
voltage specification. The specifications have been set such that one voltage regulator can work
with all supported frequencies.
Individual processor VID values may be calibrated during manufacturing such that two devices at
the same speed may have different VID settings.
The processor uses six voltage identification pins, VID[5:0], to support automatic selection of
power supply voltages.
A '1' in this table refers to a high voltage level and a '0' refers to low voltage level. If the processor
socket is empty (VID[5:0] = x11111), or the voltage regulation circuit cannot supply the voltage
that is requested, it must disable itself. See the Voltage Regulator-Down (VRD) 10.0 Design
Guidelines for Desktop Socket 478 for more details.
Power source characteristics must be guaranteed to be stable when the supply to the voltage
regulator is stable.
The processor's Voltage Identification circuit requires an independent 1.2 V supply and some other
power sequencing considerations.
14
Core Frequency
(133 MHz BCLK/533 MHz FSB)
1/14
1/15
1/16
1/17
1/18
1/19
1/20
1/21
Table 3 specifies the voltage level corresponding to the state of VID[5:0].
(200 MHz BCLK/800 MHz FSB)
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
2.80A GHz
Core Frequency
Notes
2.80E GHz
3E GHz
3.20E GHz
3.40E GHz
RESERVED
RESERVED
RESERVED
RESERVED
Table 9 and changes with

Datasheet

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