Intel SRMK2 - Server Platform - 0 MB RAM Technical Specifications page 77

; initialization. If the mask were 0Ch. Both scanpoint_04h and
; scanpoint_08h would be executed during post.
7.3.6.1.1
Table 53 defines the bitmap for each scan point, indicating when the scan point occurs and which
resources are available (RAM, Stack, Binary Data Area, Video, Keyboard).
Table 53: User binary area scan point definitions
Scan Point
Near pointer to the User Binary
extension structure: the Mask bit is 0
if this structure is not present.
Instead of a jump instruction the scan
address (offset 5) contains a 0CB
followed by a near pointer.
If SMM is enabled in CU, the system
BIOS copies the User Binary code into
SMRAM. The part of the User Binary
that is executed on SMI will be
executed in SMRAM. The SMI handler
will not make far calls because of
security concerns. The User Binary
can be used to handle OEM-specific
SMI events that a standard SMI
handler does not know about. This is
done in order to minimize the SMI
latency. This scan only occurs as a
result of an SMI (during SMM). This
routine is executed after all other SMI
detection routines if the standard
detection routines cannot handle the
SMI.
This scan occurs immediately after
video initialization.
This scan occurs immediately before
video initialization
This scan occurs on POST error. On
entry, BX register contains the
number of the POST error
This final scan occurs immediately
before the INT 19 for normal boot and
allows you to completely circumvent
the normal INT 19 boot if desired.
This scan occurs immediately before
the normal external ROM scan. This is
just before boot, but prior to the scan
for external ROMs and the scan for
conventional BIOS in User Binary.
This scan occurs immediately after
the "normal" User Binary area scan.
Intel ® SRMK2 Internet Server Technical Product Specification
Scan Point Definitions
Mask RAM/Stack/BDA
01h Not applicable
02h A stack is assured. In addition, the
part of SMRAM that the User Binary
is copied to can be used for storing
data. A User Binary implementation
can reserve some bytes for data
storage. These locations can only
be written to while in SMM.
Remember, this is SMRAM and only
accessible when in SMM. It will
persist between SMM invocations
(but not across resets or power-
downs). The processor is in real
mode at this point.
04h Yes
08h Yes
10h Yes
20h Yes
40h Yes
80h Yes
Video/Keyboard
Not applicable
Video memory and INT 10h
services are not
accessible since SMRAM
is mapped on top of where
video RAM usually is.
Keyboard services are not
available through BIOS,
although port accesses to
the keyboard are possible.
All the restrictions that are
placed on SMM code
apply.
Yes
No
Yes
Yes
Yes
Yes
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