Intel SRMK2 - Server Platform - 0 MB RAM Technical Specifications page 68

204h MTRRphysBase2
205h MTRRphysMask2
206h MTRRphysBase3
207h MTRRphysMask3
208h MTRRphysBase4
209h MTRRphysMask4
20Ah MTRRphysBase5
20Bh MTRRphysMask5
20Ch MTRRphysBase6
20Dh MTRRphysMask6
20Eh MTRRphysBase7
20Fh MTRRphysMask7
250h MTRRfix64k_00000
258h MTRRfix16k_80000
259h MTRRfix16k_A0000
268h MTRRfix4k_C0000
269h MTRRfix4k_C8000
26Ah MTRRfix4k_D0000
26Bh MTRRfix4k_D8000
26Ch MTRRfix4k_E0000
26Dh MTRRfix4k_E8000
26Eh MTRRfix4k_F0000
26Fh MTRRfix4k_F8000
2FFh MTRRdefType
7.3.2.2 Cache State on Boot
The BIOS looks at a bit in CMOS to determine if the system cache should be enabled or disabled.
If the cache is enabled, the cache controller in the processor is initialized in a consistent manner
consistent with the chipset.
7.3.2.3 Option ROM Shadowing
All on-board adapter ROMs (stored in compressed form in the system Flash ROM), and PCI
adapter ROMs are shadowed into RAM in the ISA-compatible ROM adapter memory space
between C0000h to DFFFFh. PCI BIOS ROMs are always shadowed. Typically, the video
BIOS is shadowed at C0000h if a video controller is present.
7.3.2.4 Memory Speed Optimization
The BIOS detects the system memory speed and bus speed and optimizes the memory controller
for the best performance. The system bus speed can be determined by using the processor
internal speed and the bus ratio. The memory DIMM speed can be determined using its ID.
Using this information the BIOS can set up the memory controller register for the best
performance.
Intel ® SRMK2 Internet Server Technical Product Specification
Physical Address Base 2
Physical Address Mask 2
Physical Address Base 3
Physical Address Mask 3
Physical Address Base 4
Physical Address Mask 4
Physical Address Base 5
Physical Address Mask 5
Physical Address Base 6
Physical Address Mask 6
Physical Address Base 7
Physical Address Mask 7
Fixed range for 00h - 7Fh segment in 64KB block
Fixed range for 80h - 9Fh segment in 16KB block
Fixed range for A0h - BFh segment in 16KB block
Fixed range for C0h segment in 4KB block
Fixed range for C8h segment in 4KB block
Fixed range for D0h segment in 4KB block
Fixed range for D8h segment in 4KB block
Fixed range for E0h segment in 4KB block
Fixed range for E8h segment in 4KB block
Fixed range for F0h segment in 4KB block
Fixed range for F8h segment in 4KB block
Default memory type and global enable flags
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0606060606060606h
0606060606060606h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0505050505050505h
0505050505050505h
00C00h
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