Performance Features - Intel SRMK2 - Server Platform - 0 MB RAM Technical Specifications

overwrite the existing update with a new release. These functions can be accessed from real
mode by executing INT 15 with AX=0xD042. The corresponding 16-bit protected mode interface
is not implemented. The BIOS performs all the recommended security checks before validating
an update. See Section 14.2 for information about the Pentium
Guide.
7.3.1.6 Processor Clock Ratio Settings and CMOS Clear
SRMK2 will support all speeds of the Intel Pentium III processors. Processor speeds and,
therefore, clock ratios are hard-coded within the processor and no jumpers are required. See
section 3.3 for a list of supported processors.
7.3.1.7 Boot Splash Screen
The SRMK2 BIOS will include default Intel logo that can be displayed during BIOS POST.
The display is optional.
If the QuietBoot option is disabled via BIOS setup, the BIOS displays the usual POST screen,
including the memory count and the processor information during POST. If the QuietBoot option
is enabled and a valid logo is detected, the BIOS displays the logo during POST and suppresses
the usual POST screen.
The user may hit the <Escape> key to switch to the POST diagnostic screen from the logo.
Unlike previous platforms, the BIOS does not erases the logo when option ROMs are scanned.
Since option ROMs expect the video to be in text mode, the BIOS emulates text mode. The
option ROM screen is restored if the user presses <Escape> key. The ROM screen is restored if
the BIOS detects any key combination including <control> or <alt> key during option ROM scan
because many option ROMs employ such a key combination to enter their setup. While the splash
logo is displayed, the video is in graphics mode and BIOS console redirection is disabled. OEMs
can customize the logo.

7.3.2 Performance Features

For enhanced performance, the BIOS sets up the L2 cache controller for the Pentium
processor and performs option ROM shadowing.
7.3.2.1 L2 cache Initialization
To boost system performance, the processor contains an L2 cache and cache controller, which
previously had been handled by external devices. The BIOS programs the processor's L2 cache
controller in a manner that is consistent with the chipset. The L2 cache is tested as a part of the
processor BIST. The BIOS detects the cache size and cache type (ECC or non-ECC), and
programs the cache controller accordingly before performing any cache operations. Table 48
describes the default values loaded in the MTR registers.
Offset Name
0FEh MTRRCAP
200h MTRRphysBase0
201h MTRRphysMask0
202h MTRRphysBase1
203h MTRRphysMask1
Intel ® SRMK2 Internet Server Technical Product Specification
Table 48: Memory type range register table
Description
Capability MSR, RO: VCNT, FIX, USWC
Physical Address Base 0
Physical Address Mask 0
Physical Address Base 1
Physical Address Mask 1
Pro Processor BIOS Writer's
®
III
®
Default
0508h
00006h
00FFE000800h
0000h
0000h
67