Table 2. Ez80 ® Development Platform Peripheral Bus Connector - ZiLOG eZ80F92 User Manual

eZ80F92 Development Kit
User Manual
14
Pin # Symbol
31 CS0
32 CS1
33 CS2
34 D0
35 D1
36 D2
37 D3
38 D4
39 D5
40 GND
41 D7
42 D6
43 MREQ
44 IORQ
45 GND
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80F92 Module Schematics
through 64.
2. The Power and Ground nets are connected directly to the eZ80F92 device.
3. External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF
to satisfy the timing requirements for the eZ80
either V
DD
reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in
the eZ80F91's Peripheral Power-Down Register.
Operational Description
Downloaded from Elcodis.com electronic components distributor
Table 2. eZ80
Peripheral Bus Connector Identification—JP1* (Continued)
Signal Direction
Input
Input
Input
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
or GND, depending on their inactive levels to reduce power consumption and to
®
Development Platform
Active Level
Low
Low
Low
Low
Low
®
CPU. All unused inputs should be pulled to
PRELIMINARY
2
eZ80F92 Signal
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
on pages 62
UM013904-0203