ZiLOG eZ80F92 User Manual page 32

eZ80F92 Development Kit
User Manual
22
Signal
PC[7:0]
ID_[2:0]
CON_DIS
Reserved
PD[7:0]
PB[7:0]
Note: *All of the signals are driven directly by the CPU.
Operational Description
Downloaded from Elcodis.com electronic components distributor
Table 4. GPIO Connector J6* (Continued)
Pin # Function
39,41,43, Port C, Bit [7:0]
45,47,49,
51,53
®
6,8,10 eZ80
Development
Platform ID
12 Console Disable
16,18
22,24,26, Port D, Bit[7:0]
28,30,32,
34,36
40,42,44, Port B, Bit[7:0]
46,48,50,
52,54
Direction Notes
Bidirectional
Output
Input If a shunt is installed between
pins 12 and 14, the Console
function on the eZ80
Development Platform is
disabled.
Bidirectional
Bidirectional
PRELIMINARY
®
UM013904-0203