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ZiLOG eZ80L92 User Manual

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eZ80L92 Development Kit
User Manual
PRELIMINARY
UM012906-0103
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126
Telephone: 408.558.8500 • Fax: 408.558.8300 •
www.ZiLOG.com

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  • Page 1 Development Kit User Manual PRELIMINARY UM012906-0103 ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126 Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com...
  • Page 2 Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. ©2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded.

  • Page 3: Safeguards

    Development Kit User Manual Safeguards The following precautions must be observed when working with the devices described in this document. Caution: Always use a grounding strap to prevent damage resulting from electrostatic discharge (ESD). UM012906-0103 PRELIMINARY Safeguards...
  • Page 4 Development Kit User Manual Safeguards PRELIMINARY UM012906-0103...

  • Page 5: Table Of Contents

    Operational Description ........10 eZ80L92 Module Interface ....... 10 Application Module Interface .
  • Page 6 Module ........

  • Page 7: List Of Figures

    The eZ80L92 Module ........6...
  • Page 8 Device ........
  • Page 9 Development Kit User Manual List of Tables ® Table 1. eZ80 Development Platform Hardware Specifications . . 2 ® Table 2. eZ80 Development Platform Peripheral Bus Connector Identification—JP11 ......12 ®...
  • Page 10 Development Kit User Manual ® Table 24. DC Current Characteristics of the eZ80 Development Platform with Different Module Loads ....42 Table 25. Ethernet Connector Pin Assignments ....48...

  • Page 11: Introduction

    User Manual Introduction The eZ80L92 Development Kit provides a general-purpose platform for evaluating the capabilities and operation of ZiLOG’s eZ80L92 micropro- cessor. The eZ80L92 Development Kit features two primary boards: the ® eZ80 Development Platform and the eZ80L92 Module. This arrange- ment provides a full development platform when using both boards.

  • Page 12: Hardware Specifications

    9 VDC eZ80 Development Platform Overview ® The purpose of the eZ80L92 Development Kit is to provide the developer ® with a set of tools for evaluating the features of the eZ80 family of devices, and to be able to develop a new application before building appli- ®...
  • Page 13 TCP/IP network, allowing easy system monitoring and control, and effortless processor code updates. The address bus, data bus, and all eZ80L92 Module control signals are ® buffered on the eZ80 Development Platform to provide sufficient drive capability.

  • Page 14: Figure 1. Ez80 ® Development Platform Block Diagram With

    Development Kit User Manual Peripheral Device Signals Peripheral Device Signals eZ80F92 Address Bus Address Bus E-NET Module Data Bus Data Bus Interface RS232-0 (Console) SRAM EMAC Ethernet (512 KB RS485 up to 2 MB) RS232-1 (Modem) Flash (1 MB)
  • Page 15 Decoder. C. Debug interface. ® Figure 2. The eZ80 Development Platform Figure 3 is a photographic representation of the eZ80L92 Module seg- mented into its key blocks, as shown in the legend for the figure. ® UM012906-0103 PRELIMINARY eZ80 Development Platform Overview...

  • Page 16: Figure 3. The Ez80L92 Module

    Note: Key to blocks A–C. A. eZ80L92 Module interfaces. B. CPU and memory. C. Ethernet connection. D. IrDA transceiver. Figure 3. The eZ80L92 Module ® The structures of the eZ80 Development Platform and the eZ80L92 Module are illustrated in the Schematic Diagrams starting on page 63.

  • Page 17: Ez80 ® Development Platform

    ® The eZ80 Development Platform consists of seven major hardware blocks. These blocks, listed below, are diagrammed in Figure 4. • eZ80L92 Module interface (2 female headers) ® • Power supply for the eZ80 Development Platform, the eZ80L92 Module, and application modules •...

  • Page 18: Figure 4. Basic Ez80

    Development Kit User Manual Peripheral Device Signals Address Bus E-NET Module Data Bus Interface RS232-0 (Console) SRAM (512 KB RS485 up to 2 MB) RS232-1 (Modem) Embedded Modem (7x5 matrix) Push- buttons GPIO EEPROM Address Decoder Register Application Module Headers ®...

  • Page 19: Physical Dimensions

    Development Kit User Manual Physical Dimensions ® The dimensions of the eZ80 Development Platform PCB is 177.8mm x182.9mm. The overall height is 38.1mm. See Figure 5. 175.3 mm 114.3 mm 43.2 mm 96.5 mm 55.9 mm 157.5 mm 167.6 mm 5.1 mm...

  • Page 20: Operational Description

    Development Platform. The purpose of the eZ80 Development Platform is to provide the application developer with a tool to evaluate the features of the eZ80L92 device and to develop an application without building additional hardware. eZ80L92 Module Interface The eZ80L92 Module interface provides easy connection of the eZ80L92 ®...

  • Page 21: Figure 6. Ez80 ® Development Platform Peripheral Bus Connector Pin Configuration-Jp1

    Development Kit User Manual V3.3_EXT GND_EXT A1 6 GND_EXT DIS_FLASH DIS_ETH V3.3_EXT GND_EXT MREQ IOREQ GND_EXT INSTRD BUSACK BUSREQ HEADER 25X2 IDC50 ® Figure 6. eZ80 Development Platform Peripheral Bus Connector Pin Configuration—JP1 UM012906-0103 PRELIMINARY Operational Description...

  • Page 22: Table 2. Ez80 ® Development Platform Peripheral Bus Connector Identification-Jp11

    The entire interface is represented in the eZ80L92 Module Schematics on pages 64 through 2. The Power and Ground nets are connected directly to the eZ80L92 device. Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be ®...
  • Page 23 The entire interface is represented in the eZ80L92 Module Schematics on pages 64 through 2. The Power and Ground nets are connected directly to the eZ80L92 device. Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be ®...
  • Page 24 The entire interface is represented in the eZ80L92 Module Schematics on pages 64 through 2. The Power and Ground nets are connected directly to the eZ80L92 device. Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be ®...
  • Page 25 The entire interface is represented in the eZ80L92 Module Schematics on pages 64 through 2. The Power and Ground nets are connected directly to the eZ80L92 device. Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be ®...

  • Page 26: Figure 7. Ez80 ® Development Platform I/O Connector Pin Configuration-Jp2

    Development Kit User Manual I/O Connector Figure 7 illustrates the pin layout of the I/O Connector in the 50-pin ® header, located at position JP2 of the eZ80 Development Platform. Table 3 describes the pins and their functions. GND_EXT...

  • Page 27: Table 3. Ez80 ® Development Platform I/O Connector Identification-Jp21

    1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from this table. The entire interface is represented in the eZ80L92 Module Schematics on pages 64 through 2. The Power and Ground nets are connected directly to the eZ80L92 device. UM012906-0103 PRELIMINARY Operational Description...
  • Page 28 1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from this table. The entire interface is represented in the eZ80L92 Module Schematics on pages 64 through 2. The Power and Ground nets are connected directly to the eZ80L92 device. Operational Description PRELIMINARY UM012906-0103...
  • Page 29 64 through 2. The Power and Ground nets are connected directly to the eZ80L92 device. Almost all of the connectors’ signals are received directly from the CPU. Four input signals, in particular, offer options to the application developer by disabling certain functions of the eZ80L92 Module.

  • Page 30: Application Module Interface

    Flash boot block of the eZ80L92 Module. Disable IrDA When the DIS_IrDA input signal is pulled Low, the IrDA transceiver, located on the eZ80L92 Module, is disabled. As a result, UART0 can be ® used with the RS232 or the RS485 interfaces on the eZ80 Development Platform.

  • Page 31: Table 4. General-Purpose Port Connector J6

    Development Kit User Manual ® face requires that the eZ80L92 Module also be mounted on the eZ80 Development Platform, because it (the eZ80L92 Module) contains the eZ80L92 microprocessor. To mount an application module, use the two male headers J6 and J8.
  • Page 32 Development Kit User Manual Table 4. General-Purpose Port Connector J6* (Continued) Signal Pin # Function Direction Notes PC[7:0] 39,41,43, Port C, Bit [7:0] Bidirectional 45,47,49, 51,53 ® ID_[2:0] 6,8,10 eZ80 Output Development Platform ID CON_DIS Console Disable Input If a shunt is installed between pins 12 and 14, the Console ®...

  • Page 33: I/O Functionality

    Development Kit User Manual Table 5. CPU Bus Connector J8* Signal Pin # Function Direction A[0:7] 3–10 Address Bus, Low Byte Output A[8:15] 13–20 Address Bus, High Byte Output A[16:23] 23–30 Address Bus, Upper Byte Output READ Signal Output...

  • Page 34: Table 6. Led And Port Emulation Addresses

    Development Kit User Manual Table 6 lists the memory map addresses to registers that allow access to the above functions. The register at address controls general-pur- 800000h pose port output control and LED anode register functions. The register at...

  • Page 35: Table 8. General-Purpose Port Data Register

    Development Kit User Manual Table 7. LED Anode/General-Purpose Port Output Control Register (Continued) Bit # Function Anode Col 6 Anode Col 6 GPIO Output The GPIO Data Register receives inputs or provides outputs for each of the seven general-purpose port lines, depending on the configuration of the port.

  • Page 36: Table 9. Bit Access To The Led Cathode, Modem, And Triggers

    Development Kit User Manual LED Matrix ® The one 7x5 LED matrix device on the eZ80 Development Platform is a memory-mapped device that can be used to display information, such as programmed alphanumeric characters. For example, the LED display...
  • Page 37 Cathode Row 1 Modem RST Trig 1 Trig 2 An LED display sample program is shipped with the eZ80L92 Develop- ® ment Kit. Please refer to the eZ80 Webserver-i Quick Start Guide (QS0015) or to the Tutorial section in the ZDS II User Manual (UM0123).

  • Page 38: Embedded Modem Socket Interface

    Development Kit User Manual Ground Trigger output Trig2 Trig1 Figure 8. Trigger Pins J21 and J22 Bits 6 and 7 in Table 9 are the control bits for the user triggers. If either bit is a 1, the corresponding Trig1 and Trig2 signals are driven High. If either bit is 0, the corresponding Trig1 and Trig2 signals are driven Low.

  • Page 39: Figure 9. Embedded Modem Socket Interface-J1, J5, And J9

    Development Kit User Manual Figure 9. Embedded Modem Socket Interface—J1, J5, and J9 Table 10. Connector J5 Pin Symbol Description M-TIP Telephone Line Interface—TIP. M-RING Telephone Line Interface—RING. UM012906-0103 PRELIMINARY Operational Description...

  • Page 40: Table 11. Connector J9

    Development Kit User Manual Table 11. Connector J9 Pin Symbol Description MRESET Reset, active Low, 50–100ms. Closure to GND for reset. Ground. DCD indicator; can drive an LED anode without additional circuitry. RxD indicator; can drive an LED anode without additional circuitry.

  • Page 41: Ez80 ® Development Platform Memory

    The phone line connection for the modem is for the United States only. Connecting the modem outside of the U.S. requires modification. The tested modem for this eZ80L92 Development Kit is a Conexant socket modem, part number SF56D/SP. Information about this modem and its inter- face is available in the SmartSCM SocketModem data sheet (Doc.
  • Page 42 ® A memory map of the eZ80 CPU is illustrated in Figure 10. Flash mem- ory and SRAM on the eZ80L92 Module are addressed when CS0 and CS1 ® are active Low. SRAM on the eZ80 Development Platform is addressed when CS2 is active Low.

  • Page 43: Figure 10. Memory Map Of The Ez80

    Development Kit User Manual FFFFFFh DFFFFFh SRAM Memory up to 2 MB C7FFFFh E-NET Module SRAM C00000h BFFFFFh Main Board SRAM (512 KB) B80000h Expansion SRAM Memory up to 1.5 MB 80FFFFh 800000h 7FFFFFh Expansion Module Up to 4 MB...

  • Page 44: Leds

    The eZ80 Development Platform provides user controls in the form of push buttons. These push buttons serve as input devices to the eZ80L92 microprocessor. The programmer can use them as necessary for applica- tion development. All push buttons are connected to the general-purpose port pins.

  • Page 45: Jumpers

    Table 13. J2—DIS_IrDA Shunt Status Function Affected Device IrDA interface disabled UART0 is configured to work with the RS232 or the RS485 interfaces. IrDA interface enabled The IrDA and UART0 interfaces on the eZ80L92 Module perform their functions. UM012906-0103 PRELIMINARY Operational Description...

  • Page 46: Table 14. J3-Dis_Em

    See Table 15. Table 15. J7—FlashWE Shunt Status Function Affected Device The Flash boot sector of the eZ80L92 Flash boot sector of the eZ80L92 Module is write-protected. Module. The Flash boot sector of the eZ80L92 Flash boot sector of the eZ80L92 Module is enabled for writing or Module.

  • Page 47: Table 16. J11-Dis_Flash

    When the shunt is placed, access to the Flash device is disabled/pre- vented. See Table 16. Table 16. J11—DIS_Flash Shunt Status Function Affected Device All access to Flash on the eZ80L92 Flash on eZ80L92 Module. Module is disabled. Flash on the eZ80L92 Module is Flash on eZ80L92 Module. enabled. Jumper J12 The J12 jumper connection controls the selection of a 5V or 3VDC power supply to the embedded modem, if an embedded modem is used.

  • Page 48: Table 18. J14-Ri

    Development Kit User Manual Jumper J14 The J14 jumper connection controls the polarity of the Ring Indicator. See Table 18. Table 18. J14—RI Shunt Status Function Affected Device 1–2 The Ring Indicator for UART1 is inverted. UART1. 2–3 The Ring Indicator for UART1 is not inverted.

  • Page 49: Table 20. J16-Rs485_2_En

    Development Kit User Manual Jumper J16 The J16 jumper connection controls the selection of the RS485 circuit. However, UART1 MODEM interface and the socket modem interface are disabled if the RS485 circuit is enabled. When the shunt is placed, the RS485 circuit is enabled.

  • Page 50: Connectors

    ZPAKII emulator, PC serial ports, external modems, the con- sole, and LAN/telephone lines. J6 and J8 are the headers, or connectors, that provide pin-outs to connect any external application module, such as ZiLOG’s Thermostat Applica- tion Module. Connector J6 The J6 connector provides pin-outs to make use of GPIO functionality.

  • Page 51: Console

    Connector P2 is the RS232 terminal, which can be used for observing the console output. P2 can be connected to the HyperTerminal if required. Modem Connector P3 provides a terminal for connecting an external modem, if used with the eZ80L92 Development Kit. RS485 functionality will be ® available in future eZ80 devices.
  • Page 52 Development Kit User Manual of the average current requirement when different combinations of these ® application modules are plugged in to the eZ80 Development Platform. The receiver supply current is 90–150µA and the transmitter supply cur- rent is 260mA when the LED is active. The measurements of current that are shown in Table 24 are for the user’s reference.
  • Page 53 Development Kit User Manual Table 24. DC Current Characteristics of the ® eZ80 Development Platform with Different Module Loads (Continued) Current Platform/Modules Configurations Requirement (mA) Status ® eZ80 Development Platform, eZ80L92 When the LED demo is Module, and Thermostat Application running.

  • Page 54: Ez80L92 Module

    Figure 1 on page 4. ® The eZ80L92 Module is developed to be a plug-in module to the eZ80 Development Platform. This small-footprint module provides a CPU, RAM, Flash memory, an IrDA transceiver, and an Ethernet Media Access Controller (EMAC).

  • Page 55: Figure 11. Physical Dimensions Of The Ez80L92 Module

    Development Kit User Manual 63.5 mm 16 mm 8.5 mm Link 13.7 mm 8.3 mm LEDs max. 2.54 mm 16.3 mm RJ45 9 mm 3.5 mm Top View 64 mm 9 mm IrDA 2.7 mm 6.2 mm 7 mm 55.88 mm...

  • Page 56: Figure 12. Top Layer

    Development Kit User Manual Figure 12 illustrates the top layer silkscreen of the eZ80L92 Module. Figure 12. Top Layer Functional Description PRELIMINARY UM012906-0103...

  • Page 57: Operational Description

    Figure 13. Bottom Layer Operational Description The purpose of the eZ80L92 Module as a feature of the eZ80L92 Devel- opment Kit is to provide the application developer with a plug-in tool to evaluate the EMAC, memory, IrDA, and other features of the eZ80L92 device.
  • Page 58 Ethernet LEDs There are two green LEDs, a Link LED and a LAN LED, that are located adjacent to each other on the eZ80L92 Module. A steady LAN LED (top) indicates received link pulses from the 10Base-T Ethernet. This LAN LED should be ON if RX+ is connected to TX+ and RX–...
  • Page 59 HWSleepE modes, the chip draws lower current, because only the receiver is operating. A zero-Ohm resistor at position R14 on the eZ80L92 Development Kit is required for this function. If LAN activity is detected, the LANACT signal is pulled Low. The LANACT is connected to GPIO input PD6 and can be used in interrupt edge-detection mode to wake up and reinitialize the Ethernet chip.

  • Page 60: Ez80L92 Module Memory

    This addressing structure provides 1MB of contiguous SRAM for imme- diate use. SRAM Memory The eZ80L92 Module features 512KB of fast SRAM. Access speed is typically 12ns or faster, allowing zero-wait-state operation at 48MHz. With the CPU at 48MHz, onboard SRAM can be accessed with zero wait states in eZ80 mode.
  • Page 61 3/16 pulse generator. Another signal that is used in the eZ80L92 Module’s IrDA system is Shut_Down (SD). The SD pin is connected to PD2 on the eZ80L92 Mod- ule. The IrDA control software on the user’s wireless device must enable this pin to wake the IrDA transceiver.

  • Page 62: Figure 14. Irda Hardware Connections

    RxD input. Bit 1, the Receive Enable bit, is used to block data from filling up the Receive FIFO when the eZ80L92 Module is transmitting data. Because IrDA data passes through the air as a light source, transmitted data can also be received.

  • Page 63: Dc Characteristics

    Development Platform, current requirements change. Please see Table 24 on page 42 to reference current consumption values for these different module combinations. A 0.1-Farad capacitor is provided on the eZ80L92 Module as a short-term battery backup for the RTC (see the eZ80L92 Module Schematics). The part number of the capacitor made by Panasonic is EECS0HDV.

  • Page 64: Mounting The Module

    fit. Pin 1 of ® JP1 on the eZ80L92 Module must align with pin 1 of JP1 on the eZ80 Development Platform; Pin 1 of JP2 on the eZ80L92 Module must align ®...

  • Page 65: Figure 16. Inserting A New Plug Configuration

    Development Kit User Manual 3. Select the plug configuration appropriate for your location, and insert it into the slot formerly occupied by the previous plug configuration. 4. Push the new plug configuration down until it snaps into place, as indicated in Figure 16.

  • Page 66: Zpakii

    JTAG will be supported in the next offering of eZ80 products. Application Modules ZiLOG offers the Thermostat Application module, which can be used for evaluating and developing process control and simple I/O applications. The Thermostat Application module is equipped with an LCD display that can be used to display process control and other physical parameters.

  • Page 67: Zds Ii

    Development Kit User Manual ZDS II ZiLOG Developer Studio II (ZDS II) Integrated Development Environ- ment is a complete stand-alone system that provides a state-of-the-art ® development environment. Based on the Windows Win98SE/NT4.0- SP6/Win2000-SP2/WinXP user interfaces, ZDS II integrates a language- sensitive editor, project manager, C-Compiler, assembler, linker, librarian, ®...
  • Page 68 Development Kit User Manual Application Modules PRELIMINARY UM012906-0103...

  • Page 69: Troubleshooting

    Debug Reset + Go in ZDS. No Output on Console Port The eZ80L92 Development Kit is shipped with a Flash Loader utility that is loaded in the protected boot sector of Flash memory (U3). Upon power- ® up of the eZ80...

  • Page 70: Irda Port Not Working

    Development Kit User Manual IrDA Port Not Working If you plan on using the IrDA transceiver on the eZ80L92 Module, make sure the hardware is set up as follows: • Jumper J2 must be OFF (to enable the control gate that drives the IrDA device) •...

  • Page 71: Ip Address

    Development Kit User Manual On a Local Area Network or other network, the MAC address is the com- puter's unique hardware number. (On an Ethernet LAN, the MAC address is the same as an Ethernet address.) When it is connected to the Internet, a...

  • Page 72: Contacting Zilog Customer Support

    For valuable information about hardware and software development tools, visit ZiLOG Customer Support online. Download the latest released ver- sion of ZiLOG Developer Studio! Get the latest software updates from ZiLOG as soon as they are available! Contacting ZiLOG Customer SupportPRELIMINARY UM012906-0103...

  • Page 73: Schematic Diagrams

    Development Kit User Manual Schematic Diagrams ® eZ80 Development Platform ® Figures 17 through 21 diagram the layout of the eZ80 Development Platform. A[23:0] DO NOT USE J6_17 AND J6_35 A[23:0] MA10 MA13 9V_DC MA15 MA14 9VDC ID_2 MA18...

  • Page 74: Figure 18. Ez80 ® Development Platform Schematic Diagram, #2 Of 5

    Development Kit User Manual R6 10K Ferrite Core A[23:0] M_TIP -CS2 -CS_EX_IN I/O0 -DIS_FL -MEM_CEN1 -MEM_CEN1 I/O1 -DIS_FL -CS0 -MEM_CEN2 I/O2 -MEM_CEN2 -MEM_CEN3 -MEM_CEN3 I/O3 -MEM_CEN4 I/O4 -MEM_CEN4 -L_RD I/O5 -EM_EN I/O6 -DIS_FL I/O7 SIDACTOR P3100SB RJ14 I/O8 I/O9...

  • Page 75: Figure 19. Ez80 ® Development Platform Schematic Diagram, #3 Of 5

    Development Kit User Manual A[23:0] A[23:0] D[7:0] D[7:0] D[7:0] D[7:0] A[23:0] A[23:0] A[23:0] A[23:0] VDD0 VDD0 VDD0 VDD0 VDD1 VDD1 VDD1 VDD1 -MEM_CEN1 -MEM_CEN2 -MEM_CEN3 -MEM_CEN4 0.1uF 0.1uF 0.1uF 0.1uF VSS0 VSS0 VSS0 VSS0 VSS1 VSS1 VSS1 VSS1 D[7:0]...

  • Page 76: Figure 20. Ez80 ® Development Platform Schematic Diagram, #4 Of 5

    Development Kit User Manual 9VDC 9VDC 0.1µF LM7805C/TO220/0.5A RXE160 + C19 HEADER 5 22/10 0.1µF 0.1uF RESET TXD0 PD0_TXD0 T1IN T1OUT PWR JACK -RESET 22uF T2IN T2OUT RTS0 PD2_RTS0 T3IN T3OUT 3.3V -DIS_CON FORCEOFF VIN VOUT FORCEON INVALID + C28 LT1086-3.3/TO220 R2OUTB 22/6.3...

  • Page 77: Figure 21. Ez80 ® Development Platform Schematic Diagram, #5 Of

    Development Kit User Manual MATES WITH AMP = 749268-1 LENGTH = 5' WIRES 28 AWG ® Figure 21. eZ80 Development Platform Schematic Diagram, #5 of 5—RS-485 Cable UM012906-0103 PRELIMINARY Schematic Diagrams...

  • Page 78: Ez80L92 Module

    Development Kit User Manual eZ80L92 Module Figures 22 through 30 diagram the layout of the eZ80L92 Module. Peripherals Connector SRAM eZ80 Reset Headers IRDA_TXD IRDA_TXD D[0..7] -RESET IRDA_RXD -RESET D[0..7] D[0..7] -RESET -RESET IRDA_RXD -RESET IRDA_SD IRDA_SD A[0..23] -FLASHWE A[0..23]...

  • Page 79: Figure 23. Ez80L92 Module Schematic Diagram, #2 Of 9-100-Pin Qfp

    32.768kHz XTAL3 RTC_XIN A[0..23] A[0..23] A[0..23] 18pF -CS[0..3] -CS[0..3] -CS[0..3] V3.3 V3.3 V3.3 D[0..7] D[0..7] D[0..7] PLACE CAPS CLOSE RTC_VDD TO PINS RTC_VDD 97,7,33,43 Figure 23. eZ80L92 Module Schematic Diagram, #2 of 9—100-Pin QFP eZ80L92 Device UM012906-0103 PRELIMINARY Schematic Diagrams...

  • Page 80: Figure 24. Ez80L92 Module Schematic Diagram, #3 Of 9-36-Pin Sram

    -CS1 here -CS1 N.C. 4.7k -CS1 I/O0 I/O7 I/O1 I/O6 I/O2 I/O5 I/O3 I/O4 N.C. 512kx8 SRAM SOJ36.400 100nF V3.3 74LVC04/SO 74LVC04/SO 74LVC04/SO Figure 24. eZ80L92 Module Schematic Diagram, #3 of 9—36-Pin SRAM Device UM012906-0103 PRELIMINARY Schematic Diagrams...

  • Page 81: Figure 25. Ez80L92 Module Schematic Diagram, #4 Of 9-Flash Device

    TSOP40.20MM Flashes 100nF D[0..7] D[0..7] V3.3 A[0..23] A22/A23 A[0..23] not used here -CSFLASH -CSFLASH -RESFLASH -RESFLASH -FLASHWE -FLASHWE Note: Must be pulled 'low' externally for programming. Figure 25. eZ80L92 Module Schematic Diagram, #4 of 9—Flash Device UM012906-0103 PRELIMINARY Schematic Diagrams...

  • Page 82: Figure 26. Ez80L92 Module Schematic Diagram, #5 Of 9-E-Net Module

    SIP1 V3.3 SD[0..7] RX+ <-> 3 place don't RX- <-> 6 near SA[0..3] stuff SA[0..3] CASE ETHIRQ ETHIRQ ferrite -SLEEP don't stuff -SLEEP -ACTIVE -LANLED -ACTIVE Figure 26. eZ80L92 Module Schematic Diagram, #5 of 9—E-NET Module UM012906-0103 PRELIMINARY Schematic Diagrams...

  • Page 83: Figure 27. Ez80L92 Module Schematic Diagram, #6 Of 9-Irda Reset

    SOT-23-L3 0603 alternative: Maxim MAX6802UR29D3 IR-transceiver V3.3 330nF 2R7, 0.25W IRDA_TXD IRDA_TXD 1206 (MMA 020 4) IRDA_RXD IRDA_RXD LEDA IRDA_TXD IRDA_SD IRDA_SD V3.3 IRDA_SD IRDA_RXD ZHX1810 Figure 27. eZ80L92 Module Schematic Diagram, #6 of 9—IrDA Reset UM012906-0103 PRELIMINARY Schematic Diagrams...

  • Page 84: Figure 28. Ez80L92 Module Schematic Diagram, #7 Of 9-Headers

    -INSTRD -WAIT -WAIT -WAIT -HALT_SLP -HALT_SLP -BUSREQ -BUSREQ -BUSREQ -BUSACK -BUSACK -NMI JTAG1 -NMI (JTAG0 =) JTAG2 TRIGOUT JTAG[1..4] JTAG3 JTAG[1..4] JTAG4 V3.3 V3.3_EXT V3.3_EXT GND_EXT GND_EXT Figure 28. eZ80L92 Module Schematic Diagram, #7 of 9—Headers UM012906-0103 PRELIMINARY Schematic Diagrams...

  • Page 85: Figure 29. Ez80L92 Module Schematic Diagram, #8 Of 9-Power Supply

    Power: Pmax = 1.6W Ptyp = 0.4W Current: Imax = 200mA (IrDA not in use) Imax = 460mA (IrDA in use) Ityp = 100mA PCB1 E-NET Module Rev.B 98Cxxxx-xxx Figure 29. eZ80L92 Module Schematic Diagram, #8 of 9—Power Supply UM012906-0103 PRELIMINARY Schematic Diagrams...

  • Page 86: Figure 30. Ez80L92 Module Schematic Diagram, #9 Of 9-Control Logic

    IRDA_RXD IRDA_RXD IRDA_SD IRDA_SD 0603 DIS_FL -DIS_FL -CSFLASH -CS0 -RESET -RESFLASH -RESFLASH 74LVC04/SO 74LCX32 TSSOP14 0603 -CSFLASH -CSFLASH DIS_IRDA -DIS_IRDA IRDA_SD IR_SD 74LVC04/SO 74LCX32 V3.3 TSSOP14 Figure 30. eZ80L92 Module Schematic Diagram, #9 of 9—Control Logic UM012906-0103 PRELIMINARY Schematic Diagrams...

  • Page 87: General Array Logic Equations

    Development Kit User Manual Appendix A General Array Logic Equations This appendix shows the equations for disabling the Ethernet signals pro- vided by the U10 and U15 General Array Logic (GAL) devices. U10 Address Decoder //`define idle 2'b00 //`define...
  • Page 88 Development Kit User Manual nmemen2, nmemen3, nmemen4 input nFL_DIS /* synthesis loc="P4"*/, nCS0 /* synthesis loc="P5"*/, nCS2 /* synthesis loc="P3"*/, //was 23 /* synthesis loc="P6"*/, /* synthesis loc="P7"*/, /* synthesis loc="P9"*/, /* synthesis loc="P10"*/, /* synthesis loc="P11"*/, /* synthesis loc="P12"*/, /* synthesis loc="P13"*/,...

  • Page 89: U15 Address Decoder

    Development Kit User Manual wire nCS_EX, nmemen1, nmemen2, nmemen3, nmemen4; //wire MOD_DIS = ((nmemen1==0)|(nmemen2==0)|(nmemen3==0)|(nmemen4==0));//if any //of the signals is Low, //Flash on the Module will be //disabled if nDIS_FL is High wire nEXP_EN = ~((nCS0==0)&(A7==0)&(A6==1));//expansion module //Flash enabled if this is 0 //wire nDIS_FL = (nFL_DIS) ? ~nEXP_EN : ~(nFL_DIS);...
  • Page 90 Development Kit User Manual // This PAL generates signals that control Expansion Module // access, LED and the general-purpose port. // This device is a GAL22LV10-5JC (5ns tpd) or equivalent with // Package = 28 pin PLCC module l92_em_pal(...
  • Page 91 Development Kit User Manual /* synthesis loc="P13"*/, /* synthesis loc="P27"*/, /* synthesis loc="P26"*/, nIORQ /* synthesis loc="P2"*/, /* synthesis loc="P7"*/, /* synthesis loc="P25"*/, //CS3 for CS9800 /* synthesis loc="P9"*/, nMEMRQ /* synthesis loc="P16"*/; output nEM_RD /* synthesis loc="P17"*/, nEM_WR /* synthesis loc="P18"*/,...
  • Page 92 Development Kit User Manual General Array Logic Equations PRELIMINARY UM012906-0103...

  • Page 93: Customer Feedback Form

    Customer Feedback Form If you note any inaccuracies while reading this User Manual, please copy and complete this form, then mail or fax it to ZiLOG (see Return Information, below). We also welcome your suggestions! eZ80L92 Development Kit Serial # or Board Fab #/Rev. #...
  • Page 94 Development Kit User Manual Customer Feedback Form PRELIMINARY UM012906-0103...

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