Figure 28. Schematic Diagram, #7 Of 9-Headers - ZiLOG eZ80F92 User Manual

A[0..23]
A[0..23]
D[0..7]
D[0..7]
-CS[0..3] R7
-CS[0..3]
4k7
IICSDA
IICSDA
IICSCL
IICSCL
R9
CLK_OUT
CLK_OUT
33
-DIS_FLASH
-DIS_FLASH
-CS_RAM
-CS_RAM
-DIS_IRDA
-DIS_IRDA
-FLASHWE
-FLASHWE
RTC_VDD
RTC_VDD
PB[0..7]
PB[0..7]
PC[0..7]
PC[0..7]
PD[0..7]
PD[0..7]
-RESET
-RESET
-RD
-RD
-WR
-WR
-IOREQ
-IOREQ
-MREQ
-MREQ
-INSTRD
-INSTRD
-WAIT -WAIT
-WAIT
-HALT_SLP
ALT_SLP
-BUSREQ -BUSREQ
-BUSREQ
-BUSACK
-BUSACK
-NMI
-NMI
JTAG[1..4]
JTAG[1..4]
TDO
TDO
V3.3
V3.3_EXT
V3.3_EXT
GND_EXT
GND_EXT
GND
904-0203
Downloaded from Elcodis.com electronic components distributor
GND_EXT
R8
4k7
IICSDA
IICSCL
EZ80CLK
FUTURE_USE
place near eZ80
output (PHI)
GND_EXT
R10 R33
2k2 2k2
0603 0603
JTAG1 =
(JTAG0 =)
JTAG2 =
JTAG3 =
JTAG4 =
Figure 28. Schematic Diagram, #7 of 9—Headers
PRELIMINARY
connector 1
JP1
A6
A0
1 2
A10
A3
3 4
V3.3_EXT
5 6
A8
A7
7 8
A13 A9
9 10
A15 A14
11 12
A18 A16
13 14
A19
GND_EXT
15 16
A2 A1
17 18
A11
A12
19 20
A4 A20
21 22
A5
A17
23 24
-DIS_FLASH
25 26
A21 V3.3_EXT
27 28
A22 A23
29 30
-CS0 -CS1
31 32
-CS2 D0
33 34
D1 D2
35 36
D3 D4
37 38
D5 GND_EXT
39 40
D7 D6
41 42
-MREQ -IOREQ
43 44
-RD
45 46
-WR -INSTRD
47 48
-BUSACK -BUSREQ
49 50
HEADER 25X2
IDC50
R11 R12
10k 10k
TDI
TDO
TRIGOUT
TCK
TMS
R13
4k7
eZ80F92 Development Kit
User Manual
connector 2
JP2
PB7 PB6
1 2
PB5 PB4
3 4
PB3 PB2
5 6
PB1 PB0
7 8
GND_EXT PC7
9 10
PC6 PC5
11 12
PC4 PC3
13 14
PC2 PC1
15 16
PC0 PD7
17 18
PD6 GND_EXT
19 20
PD5 PD4
21 22
PD3 PD2
23 24
PD1 PD0
25 26
TDO TDI
27 28
GND_EXT TRIGOUT
29 30
TCK TMS
31 32
RTC_VDD EZ80CLK
33 34
IICSCL
35 36
IICSDA GND_EXT
37 38
-FLASHWE
39 40
-CS3 -DIS_IRDA
41 42
-RESET -WAIT
43 44
V3.3_EXT
GND_EXT
45 46
-HALT_SLP
-NMI
47 48
V3.3_EXT
49 50
HEADER 25X2
IDC50
Schematic Diagrams
70