Figure 30. Schematic Diagram, #9 Of 9-Control Logic - ZiLOG eZ80F92 User Manual

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D[0..7]
D[0..7]
only A0,A1,A2,A3
A[0..23]
A[0..23]
are used here
PD[0..7]
PD3 and PD5
PD[0..7]
not used here
-RESET
-RESET
-WAIT
-WAIT
-RD
-RD
-WR
-WR
-CS[0..3]
-CS1 and-CS2
-CS[0..3]
not used here
R30
10k
U2B
0603
-DIS_FLASH
3
74LCX04
TSSOP14
R17
10k
U2C
0603
-DIS_IRDA
5
74LCX04
TSSOP14
-DIS_FLASH
S_FLASH
-DIS_IRDA
RDA
904-0203
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D[0..7]
A[0..23]
A0
A1
A2
A3
U2D
-RD
12
13
74LCX32
=
-CS3
-CSETH
TSSOP14
U6A
1
-WR
2
74LCX32
TSSOP14
U6B
DISABLE_FLASH
4
4
-CS0
5
74LCX32
TSSOP14
U6D
DISABLE_IRDA
6
12
PD2
=
IR_SD
13
74LCX32
TSSOP14
Figure 30. Schematic Diagram, #9 of 9—Control Logic
PRELIMINARY
=
SD[0..7]
SA[0..3]
=
SA0
=
SA1
=
SA2
=
SA3
PD4
PD7
-ETHRD
PD6
11
-WAIT
-ETHWR
3
-CSFLASH
6
IRDA_SD
11
V3.3
VDD
VSS
GND
eZ80F92 Development Kit
User Manual
SD[0..7]
SD[0..7]
SA[0..3]
SA[0..3]
-ETHRD
-ETHRD
-ETHWR
-ETHWR
=
ETHIRQ
ETHIRQ
R14
0R
-SLEEP
-SLEEP
R15
0R
-ACTIVE
-ACTIVE
don't stuff
R35
0
IOCHRDY
=
PD0
IRDA_TXD
IRDA_TXD
PD1
=
IRDA_RXD
IRDA_RXD
IRDA_SD
IRDA_SD
=
-RESET
-RESFLASH
-RESFLASH
-CSFLASH
-CSFLASH
Schematic Diagrams
72

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