ZiLOG eZ80F92 User Manual page 87

UM013904-0203
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A1,
A2,
A3,
A4,
A5,
A6,
A7,
nRD,
nCS,
nWR,
nMEMRQ,
nIORQ,
nEM_RD,
nEM_WR,
nAN_WR,
nCT_WR,
nDIS_ETH
);
input nDIS_EM /* synthesis loc="P3"*/,
nEM_EN /* synthesis loc="P4"*/,
A0 /* synthesis loc="P5"*/,
A1 /* synthesis loc="P6"*/,
A2 /* synthesis loc="P10"*/,
A3 /* synthesis loc="P11"*/,
A4 /* synthesis loc="P12"*/,
A5 /* synthesis loc="P13"*/,
A6 /* synthesis loc="P27"*/,
A7 /* synthesis loc="P26"*/,
nIORQ /* synthesis loc="P2"*/,
eZ80F92 Development Kit
PRELIMINARY
User Manual
General Array Logic Equations
77