ZiLOG eZ80F92 User Manual page 41

UM013904-0203
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2. U18, address range
3. U17, address range
If SRAM memory is installed in a different order than the above
sequence, SRAM will not be contiguous unless the user is able to change
the address decoder, U10. Memory access decoding is performed by this
address decoder, implemented in the Generic Array Logic device,
GAL22LV10D (U10).
On-Chip SRAM
The eZ80F92 device on the eZ80F92 Flash Module contains 8KB of on-
chip SRAM. Upon power-up, this SRAM is enabled and mapped to the
top 8KB of memory address space. Using the RAM Address Register,
this 8KB memory can be mapped to the top of any 64KB block. It can
also be disabled. Please see the
(PS0153) for more information.
Flash Memory
The eZ80F92 Development Kit allows off-chip Flash memories between
1MB and 4MB. This Flash memory is entirely located on the eZ80F92
Flash Module (in footprint only; as shipped from the factory, external
Flash is not installed).
Memory Map
A memory map of the eZ80
ory and SRAM on the eZ80F92 Flash Module are addressed when CS0
and CS1 are active Low. SRAM on the eZ80
addressed when CS2 is active Low.
The location of on-chip SRAM is programmable by setting the RAM
address upper byte register. The upper 8KB of any 64KB memory page
can be selected. Addresses to enabled on-chip memories assume priority
over all chip selects. Please refer to the
fication (PS0153) for more details.
PRELIMINARY
eZ80F92 Development Kit
A80000h–AFFFFFh
A00000h–A7FFFFh
eZ80F92/eZ80F92 Product Specification
®
CPU is illustrated in Figure 10. Flash mem-
®
eZ80F92/eZ80F92 Product Speci-
User Manual
Development Platform is
Operational Description
31