I/O Functionality; Table 5. Cpu Bus Connector J8 - ZiLOG eZ80F92 User Manual

Signal
A[0:7]
A[8:15]
A[16:23]
RD
RESET
BUSACK
NMI
D[0:7]
CS[0:3]
MREQ
WR
INSTRD
BUSREQ
PHI
Note: *All of the signals except BUSACK and INSTRD are driven by low-voltage
CMOS technology (LVC) drivers.
UM013904-0203
Downloaded from Elcodis.com electronic components distributor

Table 5. CPU Bus Connector J8*

Pin #
3–10
13–20
23–30
33
35
37
39
43–50
53–56
57
34
36
38
40

I/O Functionality

The eZ80190 microprocessor features General-Purpose I/O functionality
at Port A. The eZ80F92 device does not incorporate this Port A feature.
®
The eZ80 Development Platform provides additional I/O functionality,
featuring GPIO for devices without Port A, an LED matrix, a modem
reset, and two user triggers.
Function
Address Bus, Low Byte
Address Bus, High Byte
Address Bus, Upper Byte
Read Signal
Push Button Reset
CPU Bus Acknowledge Signal
Nonmaskable Interrupt
Data Bus
Chip Selects
Memory Request
WRITE Signal
Instruction Fetch
CPU Bus Request signal
Clock output of the CPU
PRELIMINARY
eZ80F92 Development Kit
User Manual
Direction
Output
Output
Output
Output
Output
Output
Input
Bidirectional
Output
Output
Output
Output
Operational Description
23