Pcie Design Guidelines Up To Gen3; Table 7-12. Pcie Interface Signal Routing Requirements Up To Gen3 - Nvidia Jetson AGX Xavier Series Design Manual

7.2.1

PCIe Design Guidelines up to Gen3

The following table details the PCIe design guidelines up to Gen3. See Section 7.2.2 for design
guidelines regarding PCIe Gen4.
Table 7-12. PCIe Interface Signal Routing Requirements up to Gen3
Parameter
Specification
Data Rate / UI Period
Configuration / Device Organization
Topology
Termination
Impedance
Trace Impedance differential / Single Ended
Reference plane
Spacing
Trace Spacing (Stripline/Microstrip)
Pair – Pair
To plane and capacitor pad
To unrelated high-speed signals
Length/Skew
Breakout region (Max Length)
Trace loss budget (for carrier board routing)
Routing direct to device
Routing to PCIe/M.2 connector
Max trace length (delay)
Direct to device on carrier board
Stripline
Microstrip
Routed to PCIe or M.2 connector
Stripline
Microstrip
Max PCB via distance from the BGA
PCB within pair (intra-pair) skew
Within pair (intra-pair) matching between
subsequent discontinuities
Differential pair uncoupled length
Via
Via placement
Max # of Vias
PTH Vias
Micro-Vias
Max Via stub length
Routing signals over antipads
Jetson AGX Xavier Series Product
Requirement Units
5.0 / 200 Gbps / ps
1 Load
Point-point
50 Ω
85 / 50 Ω
GND
3x / 4x Dielectric
3x / 4x
3x / 4x
41.9 ps
-14.5 dB/in
-10.5
491 (3383)
in (ps)
460 (27.19)
355 (2450)
333 (1969)
41.9 ps
0.075 (0.5) mm (ps)
0.075 (0.5) mm (ps)
41.9 ps
Place GND vias as symmetrically as possible to data pair vias. GND via
distance should be placed less than 1x the diff pair via pitch
2 for TX traces and 2 for RX trace
No requirement
0.4 mm
Not allowed
USB, PCIe, and UFS
Notes
2.5GHz, half-rate architecture
differential
Unidirectional,
To GND Single Ended for P and N
±15%. See note 1
TX and RX should not be routed on the
same layer. See Note 2.
Minimum width and spacing. 4x or
wider dielectric height spacing is
preferred
@ 4GHz (See TBD),
Loss: GEN3 budget – module – end
device (-22dB + 3.5.dB + 4dB)
Loss: GEN3 budget – module – end
device (-28dB + 4.24dB + 8dB)
Mid-loss PCB of 0.8dB/in (Microstrip) or
0.75dB/in (Stripline) is used. Also,
6.9ps/mm for Stripline routing and
5.9ps/mm for Microstrip.
Max distance from BGA ball to first PCB
via.
Do trace length matching before hitting
discontinuities
Longer via stubs would require review
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