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Figure 7-4.
PCIe Root Port Connection Example
SoC - PCIe
PEX
PEX_RX0_N/P
PEX_TX0_N/P
PEX_CLK1_N/P
PEX_RX2_N/P
PEX_TX2_N/P
PEX_RX3_N/P
PEX_TX3_N/P
PEX_RX4_N/P
PEX_TX4_N/P
PEX_RX5_N/P
PEX_TX5_N/P
PEX_CLK0_N/P
PEX_RX7_N/P
PEX_TX7_N/P
PEX_CLK3_N/P
PEX_RX8_N/P
PEX_TX8_N/P
PEX_RX9_N/P
PEX_TX9_N/P
PEX_CLK4_N/P
NVHS0_RX0_N/P
NVHS
NVHS0_TX0_N/P
NVHS0_RX1_N/P
NVHS0_TX1_N/P
NVHS0_RX2_N/P
NVHS0_TX2_N/P
NVHS0_RX3_N/P
_
NVHS0_TX3_N/P
NVHS0_RX4_N/P
NVHS0_TX4_N/P
NVHS0_RX5_N/P
NVHS0_TX5_N/P
NVHS0_RX6_N/P
NVHS0_TX6_N/P
NVHS0_RX7_N/P
NVHS0_TX7_N/P
PEX_CLK5_N/P
NVHS0_REFCLK_N/P
PEX
PEX_L0_CLKREQ_N
PEX_L0_RST_N
Control
PEX_L1_CLKREQ_N
PEX_L1_RST_N
PEX_L3_CLKREQ_N
PEX_L3_RST_N
PEX_L4_CLKREQ_N
PEX_L4_RST_N
PEX_L5_CLKREQ_N
PEX_L5_RST_N
PEX_WAKE_N
PEX_REFCLK1_N/P
PEX_REFCLK2_N/P
Notes:
AC Capacitors required on RX lines on carrier board if connected directly to device. They are
•
not placed on the carrier board if connected to a PCIe connector. In that cases, the AC caps are
on the PCIe add-in board.
See design guidelines for correct AC capacitor values.
•
The PCIe REFCLK inputs and PCIEx_CLK clock outputs comply to the PCIe CEM specification
•
"REFCLK DC Specifications and AC Timing Requirements." The clocks are HCSL compatible.
Jetson AGX Xavier Series Product
Jetson AGX Xavier
UPHY_RX0_N/P
UPHY_TX0_N/P
PEX_CLK1_N/P
UPHY_RX2_N/P
UPHY_TX2_N/P
UPHY_RX3_N/P
UPHY_TX3_N/P
UPHY_RX4_N/P
UPHY_TX4_N/P
UPHY_RX5_N/P
UPHY_TX5_N/P
PEX_CLK0_N/P
UPHY_RX7_N/P
UPHY_TX7_N/P
PEX_CLK3_N/P
UPHY_RX8_N/P
UPHY_TX8_N/P
UPHY_RX9_N/P
UPHY_TX9_N/P
PEX_CLK4_N/P
NVHS0_SLVS_RX0_N/P
NVHS0_TX0_N/P
NVHS0_SLVS_RX1_N/P
NVHS0_TX1_N/P
NVHS0_SLVS_RX2_N/P
NVHS0_TX2_N/P
NVHS0_SLVS_RX3_N/P
NVHS0_TX3_N/P
NVHS0_SLVS_RX4_N/P
NVHS0_TX4_N/P
NVHS0_SLVS_RX5_N/P
NVHS0_TX5_N/P
NVHS0_SLVS_RX6_N/P
NVHS0_TX6_N/P
NVHS0_SLVS_RX7_N/P
NVHS0_TX7_N/P
PEX_CLK5_N/P
NVHS0_SLVS_REFCLK_N/P
VDDIO_AO_3V3
PEX_L0_CLKREQ_N
PEX_L0_RST_N
PEX_L1_CLKREQ_N
PEX_L1_RST_N
PEX_L3_CLKREQ_N
PEX_L3_RST_N
PEX_L4_CLKREQ_N
PEX_L4_RST_N
PEX_L5_CLKREQ_N
PEX_L5_RST_N
PEX_WAKE_N
UPHY_REF CLK1_N/P
UPHY_REF CLK2_N/P
A23/A22
0.1uF
J23/J22
PCIe x1 (I/F C1). Routed to eSATA
Bridge on Carrier Board.
F17/F16
B2 0/B21
0.1uF
Lane 0
K20/K21
D21/D20
0.1uF
Lane 1
H21/H20
PCIe x4 (I/F C0). Used for M.2 Key
A19/A18
0.1uF
Lane 2
M Connector on Carrier Board.
J19/J18
C18/C19
0.1uF
Lane 3
G18/G19
E14/E15
D17/D16
0.1uF
PCIe x1 (I/F C3). Used for M.2
H17/H16
Key E on Carrier Board.
F21/F20
A14/A15
0.1uF
Lane 0
J15/J14
PCIe x2 (I/F C4). Unused on
C14/C15
0.1uF
Lane 1
Carrier Board.
G14/G15
E22/E23
D25/D24
0.22uF
Lane 0
H25/H24
B2 4/B25
0.22uF
Lane 1
K24/K25
C26/C27
0.22uF
Lane 2
G26/G27
A27/A26
0.22uF
Lane 3
J27/J26
PCIe x8 (I/F C5) or SLVS.
Used for PCIe x16 connector
D29/D28
0.22uF
Lane 4
on Carrier Board
H29/H28
B2 8/B29
0.22uF
Lane 5
K28/K29
C30/C31
0.22uF
Lane 6
G30/G31
A31/A30
0.22uF
Lane 7
J31/J30
F25/F24
For Endpoint use only
E31/E30
Control for PCIe I/F C0
E11
(M.2 Key M on Carrier Board)
D10
Control for PCIe I/F C1
D9
(eSATA Bridge on Carrier Board)
B9
Control for PCIe I/F C3
J10
(M.2 Key E on Carrier Board)
K9
Control for PCIe I/F C4
G8
(PCIe x2 – Not used on Carrier Board)
J9
Control for PCIe I/F C5
C8
(PCIe x16 Connector on Carrier Board)
H10
Shared
A8
Unused
E26/E27
Unused
F29/F28
USB, PCIe, and UFS
DG-09840-001_v2.5 | 48
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