Analog Devices LTM4683 Manual page 18

LTM4683
PIN FUNCTIONS
convention is used throughout this document: 7-bit
subordinate addressing). The lower four bits of the
LTM4683's subordinate address can be altered from this
default value by connecting a resistor from this pin to
SGND. Minimize capacitance—especially when the pin is
left open—to ensure accurate detection of the pin state.
It is recommended to use a resistor to set the address.
The ASEL_01 address will be used to address Channels
0 and 1, and a different ASEL_23 address will be used to
address Channels 2 and 3. For addressed ASEL_01, Page
0x00 corresponds to Channel 0, and Page 0x01 corre-
sponds to Channel 1. See PAGE description section. The
GUI will represent Channel 0 as U0:A0 and Channel 1 as
U0:A1. See Figure 32.
RUN0, RUN1 (B10, B11, Respectively): Enable Run
Input for Channels 0 and 1, respectively—Open-drain
input and output. The logic high on these pins enables
the respective outputs of the LTM4683. These open-
drain output pins hold the pin low until the LTM4683 is
out of reset and SV
IN_01
A pull-up resistor to 3.3V is required in the application.
The LTM4683 pulls RUN0 and/or RUN1 low, as appro-
priate, when a global fault and/or channel-specific fault
occurs whose fault response is configured to latch off and
cease regulation, issuing a CLEAR_FAULTS command via
2
I C or power-cycling SV
IN_01
module, in such cases. Do not pull RUN logic high with a
low impedance source. INTV
above UVLO. This provides power to the V
to allow programming the EERROM.
SW0 (C1-C2, D1-D2, E1-E2): Switching Node of Channel 0
Step-Down Converter Stage. Used for test purposes or
EMI-snubbing. It may be routed a short distance to a local
test point to monitor the switching action of Channel 0,
if desired, but do not route near any sensitive signals.
Otherwise, leave it electrically isolated (open).
V (C8): Internally Generated 2.5V Power Supply
DD25_01
Output Pin for Channel 0 and Channel 1 Circuits. Do not
load this pin with the external current; it is used strictly
to bias internal logic and provides current for the internal
pull-up resistors connected to the configuration-program-
ming pins. No external decoupling is required.
18
is detected to exceed V
IN_ON
is necessary to restart the
is active when SVIN_01 is
CC
and V
DD33
For more information
VTRIM1_CFG (C9): Output Voltage Select Pin for V
Fine Setting. Works in combination with VOUT1_CFG to
affect the VOUT_COMMAND (and associated output volt-
age monitoring and protection/fault-detection thresholds)
of Channel 1, at SV
the Applications Information section.) A resistor divider
from 2.5V to SGND connected to the pin will set the TRIM
value. See Table 2. Minimize capacitance especially when
the pin is left open to ensure accurate detection of the
pin state. Note that using R
VTRIM1_CFG can affect the V
PWM_MODE1[1]) and loop gain. For addressed ASEL_01,
Page 0x00 corresponds to Channel 0, and Page 0x01 cor-
responds to Channel 1. See PAGE description section.
SDA_01, SDA_23 (C10, V8): Serial Bus Data Open-Drain
Input and Output. A pull-up resistor to 3.3V is required in
the application. SDA_01 is for Channel 0 and Channel 1,
and SDA_23 is for Channel 2 and Channel 3.
ALERT_01, ALERT_23 (C11, W8): Open-Drain Digital
.
Output. A pull-up resistor to 3.3V is required in the appli-
cation only if SMBALERT interrupt detection is imple-
mented in one's SMBus system.
SHARE_CLK_01, SHARE_CLK_23 (D8, AA11): Share
Clock, Bidirectional Open-Drain Clock Sharing Pins.
Nominally 100kHz. They are used for synchronizing the
time base between multiple LTM4683s (and any other
Analog Devices products with a SHARE_CLK pin)—to
realize well-defined rail sequencing and rail tracking.
DD25
Connect the SHARE_CLK pins of all such devices together;
all devices with a SHARE_CLK pin will synchronize to the
fastest clock. A pull-up resistor to 3.3V is only required
when synchronizing the time base between devices.
VTRIM0_CFG (D9): Output Voltage Select Pin for V
Fine Setting. Works in combination with VOUT0_CFG to
affect the VOUT_COMMAND (and associated output volt-
age monitoring and protection/fault-detection thresholds)
of Channel 0, at SV
the Applications Information section.) A resistor divider
from 2.5V to SGND connected to the pin will set the
TRIM value. See Table 2. Minimize capacitance especially
when the pin is left open to ensure accurate detection
www.analog.com
power-up. (See VOUT1_CFG and
IN_01
s on VOUT1_CFG/
CONFIG
range setting (MFR_
OUT1
power-up. (See VOUT0_CFG and
IN_01
,
OUT1
,
OUT0
Rev. 0