APPLICATIONS INFORMATION
Do not put vias directly on pads, unless they are
n
capped or plated over.
Use a separate SGND copper plane for components
n
connected to signal pins. Connect SGND to GND local
to the LTM4683.
Use Kelvin sense connections across the input R
n
resistor if input current monitoring is used.
V
V
OUT0
OUT1
GND
V
IN
(a) LTM4683 Top Layer
SENSE
GND
V
V
OUT2
OUT3
GND
GND
Figure 47. Recommended PCB Layout Package, Top View
For more information
For parallel modules, tie the V
voltage-sense differential pair lines, RUNn, COMPna, and
COMPnb pins together.
The user must share the SYNC_nn, SHARE_CLK_nn,
n
FAULTn, and ALERT_nn pins of these parts. Be sure
to use pull-up resistors on FAULTn, SHARE_CLK_nn
and ALERT_nn.
Bring out test points on the signal pins for monitoring.
n
Figure 47 gives a good example of the recommended layout.
V
GND
V
V
IN
IN
4683 F47a
(b) LTM4683 Bottom Layer
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LTM4683
, V
OUTn
OSNSn
V
GND
V
V
OUT0
OUT1
OUT2
OUT3
GND
+
–
/V
OSNSn
GND
V
IN
4683 F47b
Rev. 0
77
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